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Publication years (Num. hits)
1996-2011 (11)
Publication types (Num. hits)
article(2) inproceedings(9)
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Found 11 publication records. Showing 11 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
74Ethiopia Nigussie, Juha Plosila, Jouni Isoaho Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
74Frederic Worm, Paolo Ienne, Patrick Thiran Soft self-synchronising codes for self-calibrating communication. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. Search on Bibsonomy ASP-DAC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
40Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. Search on Bibsonomy IEICE Trans. Electron. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
40Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. Search on Bibsonomy ERSA The full citation details ... 2009 DBLP  BibTeX  RDF
33Martin Simlastík, Viera Stopjaková Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. Search on Bibsonomy PATMOS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
33Daniel H. Linder, James C. Harden Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs
25Amitava Mitra, William F. McLaughlin, Steven M. Nowick Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. Search on Bibsonomy ASYNC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny Fast Asynchronous Shift Register for Bit-Serial Communication. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Victor M. Preciado Improving Cellular Nonlinear Network Computational Capabilities. Search on Bibsonomy IBERAMIA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
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