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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
74 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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74 | Frederic Worm, Paolo Ienne, Patrick Thiran |
Soft self-synchronising codes for self-calibrating communication. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
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49 | Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny |
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
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40 | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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40 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. |
IEICE Trans. Electron. |
2010 |
DBLP DOI BibTeX RDF |
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40 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. |
ERSA |
2009 |
DBLP BibTeX RDF |
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33 | Martin Simlastík, Viera Stopjaková |
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT |
33 | Daniel H. Linder, James C. Harden |
Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
Asynchronous circuitry, delay-insensitive circuitry, dual-rail encoding, LEDR, phased logic, synchronous circuitry, data flow, marked graphs |
25 | Amitava Mitra, William F. McLaughlin, Steven M. Nowick |
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. |
ASYNC |
2007 |
DBLP DOI BibTeX RDF |
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25 | Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny |
Fast Asynchronous Shift Register for Bit-Serial Communication. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
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25 | Victor M. Preciado |
Improving Cellular Nonlinear Network Computational Capabilities. |
IBERAMIA |
2002 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #11 of 11 (100 per page; Change: )
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