Search results for "LSSD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	Frank te Beest, Kees van Berkel 0001, Ad M. G. Peeters	Adding Synchronous and LSSD Modes to Asynchronous Circuits.	ASYNC	2002	DBLP DOI BibTeX RDF	design for testability, asynchronous circuits, scan test, LSSD
66	Thomas M. Storey, Bruce McWilliam	A Test Methodology for High Performance MCMs.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	LOCST, AC BIST, delay testing, boundary scan, LSSD, MCM testing
51	Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane	System-on-Chip Testability Using LSSD Scan Structures.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF
45	Kazuhiro Yamada, Yoshikazu Takahashi	Vector Memory Expansion System For T33xx Logic Tester.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	T33XX LSSD vector pattern DFT
45	Jacob Savir	Distributed Generation of Weighted Random Patterns.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	WRP, BIST, detection probability, signal probability, LSSD, SRL
45	Jacob Savir	On-Chip Weighted Random Patterns.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	WRP, BIST, detection probability, signal probability, LSSD, SRL
41	Yu Huang 0005, Keith Gallie	Diagnosis of defects on scan enable and clock trees.	DATE	2006	DBLP DOI BibTeX RDF
41	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
41	Yeong-Ruey Shieh, Cheng-Wen Wu	DC control and observation structures for analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits
30	Hugo Ruiz, Mehdi Yedroudj, Marc Chaumont, Frédéric Comby, Gérard Subsol	LSSD: a Controlled Large JPEG Image Database for Deep-Learning-based Steganalysis "into the Wild".	CoRR	2021	DBLP BibTeX RDF
30	Hugo Ruiz, Mehdi Yedroudj, Marc Chaumont, Frédéric Comby, Gérard Subsol	LSSD: A Controlled Large JPEG Image Database for Deep-Learning-Based Steganalysis "Into the Wild".	ICPR Workshops (6)	2020	DBLP DOI BibTeX RDF
30	Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Fernando Gehm Moraes, Alexandre M. Amory	An LSSD Compliant Scan Cell for Flip-Flops.	ISCAS	2018	DBLP DOI BibTeX RDF
30	Leonardo Rezende Juracy, Matheus Trevisan Moreira, Felipe Augusto Kuentzer, Alexandre de Morais Amory	Optimized Design of an LSSD Scan Cell.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
30	Kees van Berkel 0001, Ad M. G. Peeters, Frank te Beest	Adding synchronous and LSSD modes to asynchronous circuits.	Microprocess. Microsystems	2003	DBLP DOI BibTeX RDF
30	Thomas A. Ziaja	Using LSSD to test modules at the board level.	ITC	1999	DBLP DOI BibTeX RDF
30	Pamela S. Gillis, Francis Woytowich, Kevin McCauley, Ulrich Baur	Delay test of chip I/Os using LSSD boundary scan.	ITC	1998	DBLP DOI BibTeX RDF
30	Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams	Delay Test: The Next Frontier for LSSD Test Systems.	ITC	1992	DBLP DOI BibTeX RDF
30	Hideshi Maeno, Koji Nii, S. Sakayanagi, S. Kato	LSSD Compatible and Concurrently Testable Ram.	ITC	1992	DBLP DOI BibTeX RDF
30	David M. Wu	An optimized delay testing technique for LSSD-based VLSI logic circuits.	VTS	1991	DBLP DOI BibTeX RDF
30	David M. Wu, Charles E. Radke	Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits.	DAC	1991	DBLP DOI BibTeX RDF
30	Anthony Correale	Design Considerations of a Static LSSD Polarity Hold Latch Pair.	IBM J. Res. Dev.	1984	DBLP DOI BibTeX RDF
30	D. Leet, P. Shearon, R. France	A CMOS LSSD Test Generation System.	IBM J. Res. Dev.	1984	DBLP DOI BibTeX RDF
30	Edward B. Eichelberger, Eric Lindbloom	Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test.	IBM J. Res. Dev.	1983	DBLP DOI BibTeX RDF
30	Peter Hansen	New Techniques for Manufacturing Test and Diagnosis of LSSD Boards.	ITC	1983	DBLP BibTeX RDF
30	Franco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom	An LSSD Pseudo Random Pattern Test System.	ITC	1983	DBLP BibTeX RDF
30	Sumit DasGupta, Prabhakar Goel, Ron G. Walther, Tom W. Williams	A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI.	ITC	1982	DBLP BibTeX RDF
30	Kewal K. Saluja	An enhancement of lssd to reduce test pattern generation effort and increase fault coverage.	DAC	1982	DBLP DOI BibTeX RDF
30	Y. Arzoumanian, John A. Waicukauski	Fault Diagnosis in an LSSD Environment.	ITC	1981	DBLP BibTeX RDF
30	Frank C. Hsu, Peter Solecky, Robert E. Beaudoin	Structured trace diagnosis for LSSD board testing - an alternative to full fault simulated diagnosis.	DAC	1981	DBLP BibTeX RDF
24	Amit M. Sheth, Jacob Savir	Scan Latch Design for Test Applications.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	shift register latch, scan design, hardware overhead, LSSD
24	Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff	Synchronous Full-Scan for Asynchronous Handshake Circuits.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	L1L2*, DFT, asynchronous circuits, scan design, LSSD
24	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
24	Jacob Savir	Design for Testability to Combat Delay Faults.	ICCD	1999	DBLP DOI BibTeX RDF	BIST, LFSR, Delay Test, MISR, LSSD, SRL
24	Jacob Savir	Reduced Latch Count Shift Registers.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD
24	Jacob Savir	The Bidirectional Double Latch (BDDL).	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD
24	Thomas W. Williams, Kenneth P. Parker	Design for Testability - A Survey.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Built-In Logic Block Observation (BILBO), Level Sensitive Scan Design (LSSD), Random Access Scan, Scan/Set Logic, testing, test generation, self test, Signature Analysis, Scan Path
21	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Adding Testability to an Asynchronous Interconnect for GALS SoC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
21	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
21	Jacob Savir	On Chip Weighted Random Patterns.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
21	Hakim Bederr, Michael Nicolaidis, Alain Guyot	Analytic approach for error masking elimination in on-line multipliers.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	error masking elimination, online multipliers, high precision numbers, scan design approach, internal state observability, DFT approach, sequential circuits, digital arithmetic, fault coverage, multiplying circuits, area overhead
21	Sybille Hellebrand, Hans-Joachim Wunderlich	Tools and devices supporting the pseudo-exhaustive test.	EURO-DAC	1990	DBLP DOI BibTeX RDF	automatic design for testability, Pseudo-exhaustive test
21	Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto	ESTA: an expert system for DFT rule verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF