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Publication years (Num. hits)
1998-2005 (20) 2006-2008 (20) 2009-2014 (20) 2015-2018 (21) 2019-2023 (11)
Publication types (Num. hits)
article(30) inproceedings(62)
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Found 92 publication records. Showing 92 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
149Magnus Eckersand, Fredrik Franzon, Ken Filliter Using At-Speed BIST to Test LVDS Serializer/Deserializer Function. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF LVDS, BIST, differential, At-speed
83Carlos Zamarreño-Ramos, Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco LVDS interface for AER links with burst mode operation capability. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
83Ming-Dou Ker, Chien-Hua Wu Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
66Feng Zhang 0014, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu A High Speed CMOS Transmitter and Rail-to-Rail Receiver. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF LVDS rail-to-rail
63Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona LVDS Serial AER Link performance. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
63Gunjan Mandal, Pradip Mandal Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
63Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance. Search on Bibsonomy J. Intell. Robotic Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint
44Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
44Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Nidhir Kumar, Senthil N. Velu, Rajan Verma Gateway to Chips: High Speed I/O Signalling and Interface. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Donald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan Area, power, and pin efficient bus transceiver using multi-bit-differential signaling. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Rashed Zafar Bhatti, Monty Denneau, Jeff Draper 2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
27Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. Search on Bibsonomy VTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism
27G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF LVDS, DPbasic, Monotonic, IBIS
24Nanditha Maragowdanahalli Shivalingaiah, Vijaya Prakash Anamanahalli Mariyappa Performance Analysis of FinFET-Based LVDS I/O Receiver Architecture. Search on Bibsonomy SN Comput. Sci. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa Design and Trial Production FPGA based Stochastic Resonance Circuit Using LVDS and an Examination for Surface EMG Measurement. Search on Bibsonomy SICE The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Alexandros D. Bechrakis Triantafyllos, Alexandra P. Mavropoulou, Anargyros T. Baklezos, Christos N. Capsalis, Christos D. Nikolopoulos Towards the Prediction of SpaceWire Radiated Emissions Employing an LVDS Signal Emulator. Search on Bibsonomy IEEE Access The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
24Jinrong Li, Jue Wang, Xu Cheng 0002, Yicheng Zeng, Xiaoyang Zeng A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. Search on Bibsonomy ASICON The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
24Christos D. Nikolopoulos, Anargyros T. Baklezos, Stylianos Tsatalas, Christos N. Capsalis Verification of Radiated Emissions Modeling for SpaceWire/LVDS Links Routed on CFRP Ground. Search on Bibsonomy IEEE Trans. Aerosp. Electron. Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Seng Siong Lee, Lini Lee, Fabian Wai Lee Kung, Ahmed Saad, Harikrishnan Ramiah, Gim Heng Tan A Low Power High Precision Trim-Less Envelope Detector for Fail-Safe Circuit in LVDS Receiver. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Liang Xie 0004, Shunle Guo, Zhaoxi Li, Xiangliang Jin A High Speed Rail-to-Rail Operational Amplifier with Constant-gm for LVDS Receiver. Search on Bibsonomy ICCT The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Ning Qiao, Giacomo Indiveri A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
24Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. Search on Bibsonomy PRIME The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Niraj Kumar Jha, Dishank Yadav, Anuj Maheshwari, Mrigank Sharad Radiation Hardened High-Speed LVDS compliant Transceiver. Search on Bibsonomy CONIELECOMP The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Pengfei Lang, Qingfeng Shi, Zebing Xie, Hongtao Zheng, Yan Zhao Research on Intelligent Estimation Model of BER for High-Speed Image Transmission Based on LVDS Interface. Search on Bibsonomy ADHIP (2) The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Seng Siong Lee, Lini Lee, Wai Lee Kung, Ahmed Saad, Gim Heng Tan A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations. Search on Bibsonomy Microelectron. J. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Hanyang Xu, Jian Wang 0036, Jinmei Lai Design of a power efficient self-adaptive LVDS driver. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Durga Prasanth Kumar Gavara, G. Shekar Design of LVDS Transmitter with SLVDS mode for Low Power Applications in 55nm CMOS Technology. Search on Bibsonomy ICACCI The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Srikanth Jagannathan, Kumar Abhishek, Nihaar N. Mahatme, Ender Yilmaz Design of aging aware 5 Gbps LVDS transmitter for automotive applications. Search on Bibsonomy IRPS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Ning Qiao, Giacomo Indiveri A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition. Search on Bibsonomy ISCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Jayshree, G. Seetharaman Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay. Search on Bibsonomy AHS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Wei Fan, Zhelu Li, Jianxiong Xi, Lenian He, Kexu Sun, Ning Xie A 1.2 Gbps failsafe low jitter LVDS transmitter-receiver applied in CMOS image sensor. Search on Bibsonomy MOCAST The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Syed Arsalan Jawed, Ali Asghar, Khubaib Khan, Shahbaz Abbasi, Muhammad Naveed 0004, Yasir Siddiqi, Waqas Siddiqi A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. Search on Bibsonomy IEEE Trans. Biomed. Circuits Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Munish Malik, Ajay Kumar, H. S. Jatana Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. Search on Bibsonomy VDAT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories. Search on Bibsonomy MOCAST The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Jayshree, Seema Verma, Amitabh Chatterjee A methodology for designing LVDS interface system. Search on Bibsonomy ISED The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke Reduced power consumption in the FPGA-based Universal Link for LVDS communications. Search on Bibsonomy LASCAS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Giacomo Alberto Graceffa, Umberto Gatti, Cristiano Calligaro A 400 Mbps radiation hardened by design LVDS compliant driver and receiver. Search on Bibsonomy ICECS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Yuan Su, Fan Ye 0001, Junyan Ren A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke Hardware implementation of a FPGA-based universal link for LVDS communications. Search on Bibsonomy LASCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye 0001, Junyan Ren LVDS transmitter with optimized high power-efficiency 8: 1 MUX. Search on Bibsonomy ASICON The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh Methodology for optimizing ESD protection for high speed LVDS based I/Os. Search on Bibsonomy VDAT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Sultan A. Alqarni, Ahmed K. Kamal LVDS receiver with 7mW consumption at 1.5 Gbps. Search on Bibsonomy ICM The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Benjamín T. Reyes, German Paulina, Lucas Tealdi, Emanuel Labat, Raul M. Sanchez, Pablo Sergio Mandolesi, Mario Rafael Hueda A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system. Search on Bibsonomy LASCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Taras Iakymchuk, Alfredo Rosado, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Seng Siong Lee, Ahmed Saad, Lini Lee, Wai Lee Kung On-chip slew-rate control for low-voltage differential signalling (LVDS) driver. Search on Bibsonomy ISPACS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Tadeusz Satlawa, Aleksandra Drozd, Piotr Kmon Design of the ultrafast LVDS I/O interface in 40 nm CMOS process. Search on Bibsonomy MIXDES The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings. Search on Bibsonomy IEEE Trans. Biomed. Circuits Syst. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Song-Nien Tang, Chien-Ju Lee, Guo-Zua Wu Soft-IP core design of LVDS receivers for multichannel ultrasound imaging applications. Search on Bibsonomy ISCE The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Xiangyang Li Implementation and Transmission Error Handling of Multi-channel LVDS. Search on Bibsonomy EIDWT The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco A 0.35~µm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links. Search on Bibsonomy IEEE Trans. Biomed. Circuits Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Hazem Wael Marar, Khaldoon Abugharbieh, Abdel-Karim Al-Tamimi A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver. Search on Bibsonomy ICECS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration. Search on Bibsonomy IEICE Trans. Electron. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Khaldoon Abugharbieh, Shoba Krishnan, Jitendra Mohan, Varadarajan Devnath, Ivan Duzevik An Ultralow-Power 10-Gbits/s LVDS Output Driver. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Armin Tajalli, Yusuf Leblebici A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim A Distortion-Free General Purpose LVDS Driver. Search on Bibsonomy IEICE Trans. Electron. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu Design of an All-Digital LVDS Driver. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links. Search on Bibsonomy ISCAS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's. Search on Bibsonomy IEICE Trans. Electron. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Peng Chu, Zhiping Wen 0001, Lixin Yu A Novel Low-Voltage Low-Power LVDS Driver. Search on Bibsonomy IMECS The full citation details ... 2007 DBLP  BibTeX  RDF
24Vladimir Bratov, Jeb Binkley, Vladimir Katzman, John Choma Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, Jin-Fon Huang Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Panduka Wijetunga A 10.0Gb/s all-active LVDS receiver in 0.18µm CMOS technology. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona A LVDS Serial AER Link. Search on Bibsonomy ICECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Chung-Yuan Chen, Tai-Ping Sun A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application. Search on Bibsonomy ICECS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Jyh-Shin Pan, Tse-Hsiang Hsu, Hao-Cheng Chen, Jong-Woei Chen, Bing-Yu Hsieh, Hong-Ching Chen, Wei-Hsuan Tu, Chi-Ming Chang, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan-Cheng Hsiao, Chuan Liu, Lily Huang, Chia-Hua Chou, Chang-Long Wu, Meng-Hsueh Lin, Shang-Ping Chen, Brian Liu, Heng-Shou Hsu, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Sean Chien, Kuan-Hua Chao, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Yih-Shin Weng, Ming-Shiam Tsai, Kun-Hung Hsieh, Kuang-Jung Chang, Jin-Chuan Hsu, Hsiu-Chen Peng, Alex Ho Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY. Search on Bibsonomy ISSCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Chung-Yuan Chen, Jia-Hong Wang, Tai-Ping Sun A Novel Mini-LVDS Receiver in 0.35-um CMOS. Search on Bibsonomy SoCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
24Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson Low-voltage low-power LVDS drivers. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC. Search on Bibsonomy ESSCIRC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Gunjan Mandal, Pradip Mandal Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  BibTeX  RDF
24Mehdi Bathaee, Zed Mostoufi, Hamid Ghezelayagh, Anahita Afkham A 2.0 GHz 4 Mb pseudo-SRAM with on-chip BIST for refresh in 0.18u CMOS technology with LVDS output data bus drivers. Search on Bibsonomy ICECS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Andrea Boni, Andrea Pierazzi, Davide Vecchi LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Magnus Eckersand, Fredrik Franzon, Ken Filliter Using at-speed BIST to test LVDS serializer/deserializer function. Search on Bibsonomy ETW The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
24Andrea Diermeier Interfacing between LVDS and ECL. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
19Cameron D. Patterson, Steven W. Ellingson, Brian S. Martin, K. Deshpande, John H. Simonetti, Michael Kavic, Sean E. Cutchin Searching for Transient Pulses with the ETA Radio Telescope. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Direct sampling radio telescope array, FPGA cluster computing, RFI mitigation, signal dedispersion
19Boo-Young Choi, Jung-Won Han, Sung Min Park 0001, Kang-Yeob Park, Wonseok Oh 0003, J.-C. Choi A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Hans Kristian Otnes Berge, Philipp Häfliger High-Speed Serial AER on FPGA. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Adnan Gundel, William N. Carr A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Vinita V. Deodhar, Jeffrey A. Davis Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Jay Abraham, Guruprasad Rao Qualification and Integration of Complex I/O in SoC Design Flows. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
19Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF LCD displays, digital display interfaces, low-power bus encoding
19Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sébastien Laberge, Gordon W. Roberts A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
19Stephen J. Bellis, William P. Marnane A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. Search on Bibsonomy FPL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
19Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano MEMOnet : Network interface plugged into a memory slot. Search on Bibsonomy CLUSTER The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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