Search results for "Leakage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
210	Vivek De	Leakage-tolerant design techniques for high performance processors.	ISPD	2002	DBLP DOI BibTeX RDF
186	David T. Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
101	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
99	Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu	On Composite Leakage Current Maximization.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage
94	Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester	Gate-length biasing for runtime-leakage control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
94	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
93	Wei Wang, Yu Hu 0001, Yinhe Han 0001, Xiaowei Li 0001, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
91	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
82	Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma	Defocus-Aware Leakage Estimation and Control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
82	Jason Helge Anderson, Farid N. Najm	Active leakage power optimization for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
82	Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001, Wenping Wang	Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
82	Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen	Cache leakage control mechanism for hard real-time systems.	CASES	2007	DBLP DOI BibTeX RDF	cache leakage control policy, hard real-time system
81	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
79	Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic	Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines.	ISCA	2002	DBLP DOI BibTeX RDF	Dynamic Leakage Reduction
76	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
76	Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin	Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration
76	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
76	Wei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Reducing dynamic and leakage energy in VLIW architectures.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	dynamic energy, schedule slacks, compiler, VLIW architecture, leakage energy
76	Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.	DAC	2006	DBLP DOI BibTeX RDF	leakage, technology mapping, logical effort
76	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Defocus-aware leakage estimation and control.	ISLPED	2005	DBLP DOI BibTeX RDF	ACLV, yield, leakage, lithography
76	Amit Agarwal 0001, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy 0001	Leakage in nano-scale technologies: mechanisms, impact and design considerations.	DAC	2004	DBLP DOI BibTeX RDF	process variation, leakage current, circuit design
73	Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown	Analysis and Optimization of Enhanced MTCMOS Scheme.	VLSI Design	2004	DBLP DOI BibTeX RDF
70	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
70	Kamal S. Khouri, Niraj K. Jha	Leakage power analysis and reduction during behavioral synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
70	Hongliang Chang, Sachin S. Sapatnekar	Prediction of leakage power under process uncertainties.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	process variation, yield, leakage, Circuit
70	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
70	Stefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas	A simple mechanism to adapt leakage-control policies to temperature.	ISLPED	2005	DBLP DOI BibTeX RDF	hybrid leakage mechanism, thermal adaptation, drowsy cache, cache decay
69	Jie Gu 0003, John Keane 0001, Chris H. Kim	Modeling and analysis of leakage induced damping effect in low voltage LSIs.	ISLPED	2006	DBLP DOI BibTeX RDF	damping effect, supply noise, gate leakage, subthreshold leakage
67	Lei He 0001, Weiping Liao, Mircea R. Stan	System level leakage reduction considering the interdependence of temperature and leakage.	DAC	2004	DBLP DOI BibTeX RDF	microarchitecture, leakage power, temperature
67	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
64	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
64	Min Ni, Seda Ogrenci Memik	Thermal-induced leakage power optimization by redundant resource allocation.	ICCAD	2006	DBLP DOI BibTeX RDF
64	Nam Sung Kim, David T. Blaauw, Trevor N. Mudge	Quantitative analysis and optimization techniques for on-chip cache leakage power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
64	Narender Hanchate, Nagarajan Ranganathan	A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors.	VLSI Design	2004	DBLP DOI BibTeX RDF
64	Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal 0001, Chris H. Kim, Kaushik Roy 0001	Gate leakage reduction for scaled devices using transistor stacking.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
64	Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha	Topological Analysis for Leakage Prediction of Digital Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
64	Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	Reducing leakage in a high-performance deep-submicron instruction cache.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
64	Wei Zhang 0002, Bramha Allu	Reducing branch predictor leakage energy by exploiting loops.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	compiler, Branch prediction, leakage energy
64	Michele Boreale	Quantifying Information Leakage in Process Calculi.	ICALP (2)	2006	DBLP DOI BibTeX RDF	information theory, process calculi, secrecy, information leakage
64	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
64	Wei Zhang 0002, Bramha Allu	Loop-based leakage control for branch predictors.	CASES	2004	DBLP DOI BibTeX RDF	compiler, branch prediction, leakage energy
64	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
64	Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester	Statistical estimation of leakage current considering inter- and intra-die process variation.	ISLPED	2003	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
64	Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.	DAC	2003	DBLP DOI BibTeX RDF	doping profiles, leakage, tunneling, threshold voltage
64	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
63	Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector
63	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
63	Amit Agarwal 0001, Kaushik Roy 0001	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.	ISLPED	2003	DBLP DOI BibTeX RDF	diode, low leakage cache, SRAM, gate leakage
63	Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown	Efficient techniques for gate leakage estimation.	ISLPED	2003	DBLP DOI BibTeX RDF	pattern-dependent, pattern-independent, estimation, leakage, gate leakage
61	Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001	Closed-loop modeling of power and temperature profiles of FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	sub-threshold leakage, dynamic power
61	Kaviraj Chopra, Sarma B. K. Vrudhula	Implicit pseudo boolean enumeration algorithms for input vector control.	DAC	2004	DBLP DOI BibTeX RDF	power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods
58	Sung Woo Chung, Kevin Skadron	On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Low-power design, Microprocessors, Cache memories, Energy-aware systems
58	Yongpan Liu, Robert P. Dick, Li Shang, Huazhong Yang	Accurate temperature-dependent integrated circuit leakage power estimation is easy.	DATE	2007	DBLP DOI BibTeX RDF
58	Lin Yuan, Gang Qu 0001	Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimization.	ICCAD	2007	DBLP DOI BibTeX RDF
58	Lin Yuan, Gang Qu 0001	A combined gate replacement and input vector control approach for leakage current reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
58	Jun-Cheol Park, Vincent John Mooney III	Sleepy Stack Leakage Reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
58	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Runtime Leakage Minimization Through Probability-Aware Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
58	Micah G. O'Halloran, Rahul Sarpeshkar	An analog storage cell with 5e-/sec leakage.	ISCAS	2006	DBLP DOI BibTeX RDF
58	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Static leakage reduction through simultaneous Vt/Tox and state assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
58	Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001	Low-leakage robust SRAM cell design for sub-100nm technologies.	ASP-DAC	2005	DBLP DOI BibTeX RDF
58	Domenik Helms, Eike Schmidt, Wolfgang Nebel	Leakage in CMOS Circuits - An Introduction.	PATMOS	2004	DBLP DOI BibTeX RDF
58	Ge Yang 0004, Zhongda Wang, Sung-Mo Kang	Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies.	VLSI Design	2004	DBLP DOI BibTeX RDF
58	Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.	HPCA	2001	DBLP DOI BibTeX RDF
58	Daniel Eckerbert, Per Larsson-Edefors	Cycle-true leakage current modeling for CMOS gates.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
58	Kamal S. Khouri, Niraj K. Jha	Leakage Power Analysis and Reduction during Behavioral Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
58	Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy 0001	Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.	ISLPED	1998	DBLP DOI BibTeX RDF
58	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear statistical analysis for full-chip leakage power with spatial correlation.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	statistical leakage analysis, strong and weak correlation, linear, look-up table
58	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
58	Yuan-Shin Hwang, Jia-Jhe Li	Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Caches, leakage power, drowsy caches, cache decay
58	Yifan Zhu, Frank Mueller 0001	DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling.	LCTES	2007	DBLP DOI BibTeX RDF	scheduling, real-time systems, dynamic voltage scaling, leakage, feedback control
58	Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang	Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.	ISLPED	2007	DBLP DOI BibTeX RDF	post-placement optimization, scheduling, field-programmable gate array, leakage
58	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	Floorplan driven leakage power aware IP-based SoC design space exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	floorplan, leakage power, temperature
58	Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache
58	Sung Woo Chung, Kevin Skadron	Using Branch Prediction Information for Near-Optimal I-Cache Leakage.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low Power, Branch Prediction, Leakage, Instruction Cache, Drowsy Cache
58	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
58	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
58	Yan Meng, Timothy Sherwood, Ryan Kastner	Leakage power reduction of embedded memories on FPGAs through location assignment.	DAC	2006	DBLP DOI BibTeX RDF	location assignment, leakage power, embedded memory
58	Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001	Controlling leakage power with the replacement policy in slumberous caches.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	tranquility level, leakage power, replacement policy, drowsy cache
58	Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge	Total leakage optimization strategies for multi-level caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, cache memory, gate leakage
58	Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri	A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.	DAC	2005	DBLP DOI BibTeX RDF	leakage power, self-adjusting, body-biasing
58	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
58	Stefanos Kaxiras, Polychronis Xekalakis	4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors.	ISLPED	2004	DBLP DOI BibTeX RDF	4T SRAM, architecture, sensor, leakage, temperature
58	Vishal Khandelwal, Ankur Srivastava 0001	Active mode leakage reduction using fine-grained forward body biasing strategy.	ISLPED	2004	DBLP DOI BibTeX RDF	forward body biasing, leakage power optimization
58	Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester	Parametric yield estimation considering leakage variability.	DAC	2004	DBLP DOI BibTeX RDF	variability, leakage, parametric yield
58	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Tradeoffs between date oxide leakage and delay for dual Tox circuits.	DAC	2004	DBLP DOI BibTeX RDF	dual Tox circuits, leakage power
58	Ashish Srivastava, Robert Bai, David T. Blaauw, Dennis Sylvester	Modeling and analysis of leakage power considering within-die process variations.	ISLPED	2002	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
57	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
57	Cassondra Neau, Kaushik Roy 0001	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
57	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
55	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
55	Chris H. Kim, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar, Kaushik Roy 0001	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.	IOLTS	2005	DBLP DOI BibTeX RDF
55	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
54	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
52	Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min	Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs.	VLSI Design	2007	DBLP DOI BibTeX RDF
52	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.	DAC	2010	DBLP DOI BibTeX RDF	statistical analysis, spatial correlation, dynamic power
52	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Input Vector Reordering for Leakage Power Reduction in FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
52	Jun Seomun, Jae-Hyun Kim, Youngsoo Shin	Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
52	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
52	Xiaoji Ye, Yaping Zhan, Peng Li 0001	Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.	DAC	2007	DBLP DOI BibTeX RDF
52	Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester	Analytical yield prediction considering leakage/performance correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF