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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3 occurrences of 3 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 153 | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
A multilevel hierarchical interconnection structure for FPGA.  |
FPGA  |
2006 |
DBLP DOI BibTeX RDF |
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| 117 | Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez |
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
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| 91 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
A new Multilevel Hierarchical MFPGA and its suitable configuration tools. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
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| 76 | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
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| 51 | Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
Configuration tools for a new multilevel hierarchical FPGA. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
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| 40 | Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez |
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
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| 36 | Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez |
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
MFPGA, Timing balance, WDDL, Routing, Placement, Differential Power Analysis |
Displaying result #1 - #7 of 7 (100 per page; Change: )
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