Search results for "MISRs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
96	Jacob Savir	On shrinking wide compressors.	VTS	1995	DBLP DOI BibTeX RDF	wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
80	Geetani Edirisooriya, John P. Robinson	Aliasing properties of circular MISRs.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	multiple input signature analysis, test data compaction, built-in self-test, Aliasing probability
64	Joon-Sung Yang, Nur A. Touba	Enhancing Silicon Debug via Periodic Monitoring.	DFT	2008	DBLP DOI BibTeX RDF
64	Kazuhiko Iwasaki, Fumio Arakawa	An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
64	Kazuhiko Iwasaki	Analysis and proposal of signature circuits for LSI testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
59	Slawomir Pilarski	Comments on "Aliasing Properties of Circular MISRs".	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	built-in self-test, Aliasing, signature analysis, error models, test response compaction
42	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
37	Rajendra S. Katti, Rucha Sule	MISRs for Fast Authentication of Long Messages.	DSD	2013	DBLP DOI BibTeX RDF
37	Brion L. Keller, Thomas Bartenstein	Use of MISRs for compression and diagnostics.	ITC	2005	DBLP DOI BibTeX RDF
37	Geetani Edirisooriya, John P. Robinson	Authors' reply to comments on "Aliasing Properties of Circular MISRs".	J. Electron. Test.	1995	DBLP DOI BibTeX RDF
33	Kazuhiko Iwasaki, Shigeo Nakamura	Aliasing Error for a Mask ROM Built-In Self-Test.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	mask ROM, experimental faults analysis, Built-in self-test, aliasing probability, MISRs
21	Chunsheng Liu, Krishnendu Chakrabarty, Michael Gössel	An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.	DATE	2002	DBLP DOI BibTeX RDF
21	Firas Khadour, Xiaoling Sun	Fast Signature Simulation for PPSFP Simulators.	DFT	1999	DBLP DOI BibTeX RDF
21	Rodrigue Byrne	Determining Aliasing Probabilities in BIST by Counting Strings.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	response analysis architectures, compression techniques, aliasing probabilities, deterministic finite automata
21	Manoj Franklin	Fast computation of C-MISR signatures.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
21	Manoj Franklin, Kewal K. Saluja, Kyuchull Kim	Fast computation of MISR signatures.	VLSI Design	1995	DBLP DOI BibTeX RDF	MISR signatures, fast computation, test response compression, multi-input signature registers, equivalent single input circuit, logic testing, design for testability, logic design, table lookup, table lookups, shift registers, binary sequences, speedup technique, signature analyzers
21	Martin Rudolph	Feedback-testing by using multiple input signature registers.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR
21	Micaela Serra, Jon C. Muzio	Space compaction for multiple-output circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF