Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
119 | Satoshi Sugahara, Masaaki Tanaka |
Spin MOSFETs as a basis for spintronics. |
ACM Trans. Storage |
2006 |
DBLP DOI BibTeX RDF |
spin MOSFETs, spin transistors, MOSFETs, Spintronics |
66 | Zhi-Qiang Lu, Feng-Chang Lai |
Compact Modeling of MOSFETs Channel Noise for Low-Noise RF ICs Design. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
64 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
54 | Jin He 0003, Xing Zhang 0002, Ganggang Zhang, Mansun Chan, Yangyuan Wang |
A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Takahide Sato, Shigetaka Takagi, Nobuo Fujii |
Rail-to-rail OTA using a pair of single channel type MOSFETs. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Dragica Vasileska, Santhosh Krishnan, Massimo V. Fischetti |
Examining Performance Enhancement of p-Channel Strained-SiGe MOSFET Devices. |
Numerical Methods and Applications |
2006 |
DBLP DOI BibTeX RDF |
p-channel MOSFETs, bandstructure effects, quantum confinement, performance enhancement, strain |
51 | Toshiro Akino, Takashi Hamahata |
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Toshiro Akino, Kei Matsuura, Akiyoshi Yasunaga |
A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Shinji Odanaka, Akira Hiroki, Kikuyo Ohe, Kaori Moriyama, Hiroyuki Umimoto |
SMART-II: a three-dimensional CAD model for submicrometer MOSFET's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
41 | A. Madan, S. C. Bose, P. J. George, Chandra Shekhar 0001 |
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs |
41 | Yue Fu, Jin He 0003, Feng Liu, Jie Feng, Chenyue Ma, Lining Zhang |
Study on the Si-Ge Nanowire MOSFETs with the Core-Shell Structure. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
non-classical device modeling, core-shell, quantum mechanical effect, nanowire |
41 | Shinji Odanaka |
A High-Resolution Method for Quantum Confinement Transport Simulations in MOSFETs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Nikos Konofaos, G. Ph. Alexiou |
New Challenges Emerging on the Design of VLSI Circuits Made of MOSFETs Using New Gate Dielectric Materials. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Jin He 0003, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu |
A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Kaveh Shakeri, James D. Meindl |
A compact delay model for series-connected MOSFETs. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Yutao Ma, Litian Liu, Lilin Tian, Zhiping Yu, Zhijian Li |
Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Kinya Matsuda, Yoshihiko Horio, Kazuyuki Aihara |
A simulated LC oscillator using multi-input floating-gate MOSFETS. |
ISCAS (3) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele |
erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Hong June Park, Ping Keung Ko, Chenming Hu |
A charge sheet capacitance model of short channel MOSFETs for SPICE. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
39 | M. Jamal Deen |
Highly sensitive, low-cost integrated biosensors. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
BioFETs, integrated circuits, MOSFETs, noise analysis |
38 | Nor Hisham Hamid, Alan F. Murray, David I. Laurenson, Scott Roy, Binjie Cheng |
Probabilistic computing with future deep sub-micrometer devices: a modelling approach. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | E. Efthymiou, P. Rutter, P. Whiteley |
A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating. |
Microelectron. Reliab. |
2016 |
DBLP DOI BibTeX RDF |
|
30 | Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya |
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. |
CICC |
2011 |
DBLP DOI BibTeX RDF |
|
30 | Maxime Feraille |
Etude du Transport dans les Transistors MOSFETs Contraints: Modélisation Multi-échelle. (Study of Transport Properties in Strained transistors MOSFETs: Multi-scale Approach). |
|
2009 |
RDF |
|
28 | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Lining Zhang, Jin He 0003, Jian Zhang 0002, Feng Liu, Yue Fu, Yan Song, Xing Zhang |
An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
28 | J.-C. Guo, Y.-M. Lin |
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Hsiao-Chun Wu, Sameer R. Herlekar, M. Saquib, Ashok Srivastava |
Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs. |
IEEE Trans. Wirel. Commun. |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal |
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
28 | S. Kolberg, Tor A. Fjeldly, Benjamín Iñíguez |
Self-consistent 2D Compact Model for Nanoscale Double Gate MOSFETs. |
International Conference on Computational Science (4) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Jin He 0003, Xing Zhang 0002, Ganggang Zhang, Yangyuan Wang |
A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
28 | H. Kondou, Sumio Fukai, Yohei Ishikawa |
Multiple-valued SRAM with FG-MOSFETs. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Brian Swahn, Soha Hassoun |
Gate sizing: finFETs vs 32nm bulk MOSFETs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate sizing, thermal modeling, FinFET |
28 | Nele V. T. D'Halleweyn, James Benson, William Redman-White, Ketan Mistry, M. Swanenberg |
MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
28 | K. Narasimhulu, Siva G. Narendra, V. Ramgopal Rao |
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara |
An integrated multi-scroll circuit with floating-gate MOSFETs. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Junlin Zhou, Mengzhang Cheng, Leonard Forbes |
SPICE models for flicker noise in p-MOSFETs in the saturationregion. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Elmar Gondro, Peter Klein, Franz Schuler |
An analytical source-and-drain series resistance model of quarter micron MOSFETs and its influence on circuit simulation. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Jürgen Jakumeit |
Evolutionary Algorithms for the Calculation of Electron Distributions in Si-MOSFETs. |
PPSN |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller |
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
neuron MOSFET, product sum computation, systolic array, Ternary logic |
28 | Steve Shao-Shiun Chung |
A charge-based capacitance model of short-channel MOSFETs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
28 | Masaaki Tomizawa, Kiyoyuki Yokoyama, Akira Yoshii |
Nonstationary carrier dynamics in quarter-micron Si MOSFETs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
26 | Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu |
Compact Modeling of Variation in FinFET SRAM Cells. |
IEEE Des. Test Comput. |
2010 |
DBLP DOI BibTeX RDF |
multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling |
26 | Yen-Kuei Chu, Hsiu-Sheng Lin, Po-Chou Lai |
Research of a Fast High Voltage Semiconductor Switch. |
ISPA |
2010 |
DBLP DOI BibTeX RDF |
Pulse Forming Networks (PFNs), Pulse Repetition Frequency (PRF), Metal Oxide Semiconductors Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs) |
26 | Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta |
Device/circuit interactions at 22nm technology node. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs |
26 | Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw |
Low power circuit design based on heterojunction tunneling transistors (HETTs). |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
SRAM design, low power applications, tunneling transistor |
26 | Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak |
Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley |
A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Hyung-Ock Kim, Youngsoo Shin |
Analysis and optimization of gate leakage current of power gating circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Roopak Suri, C. M. Markan |
Threshold Trimming Based Design of a CMOS Programmable Operational Amplifier. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Aditya Bansal, Kaushik Roy 0001 |
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman |
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Krissanapong Nandhasri, Jitkasem Ngarmnil |
Designs of analog and digital comparators with FGMOS. |
ISCAS (1) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal |
Transistor Modeling for the VDSM Era. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
field effect transistors, parameter extraction, SPICE, device modeling |
26 | Andreas Herrfeld, Siegbert Hentschke |
Quatemary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits. |
ISMVL |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr. |
Universal MOSFET hole mobility degradation models for circuit simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
26 | C. Patrick Yue, Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr. |
Improved universal MOSFET electron mobility degradation models for circuit simulation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
26 | Franco Venturi, Enrico Sangiorgi, Rossella Brunetti, Wolfgang Quade, Carlo Jacoboni, Bruno Riccò |
Monte Carlo simulations of high energy electrons and holes in Si-n-MOSFET's. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1991 |
DBLP DOI BibTeX RDF |
|
26 | Martin Thurner, Siegfried Selberherr |
Three-dimensional effects due to the field oxide in MOS devices analyzed with MINIMOS 5. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
15 | Santi Agatino Rizzo, Nunzio Salerno |
Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Xin Li, Yifei Luo, Ruitian Wang, Zenan Shi, Fei Xiao |
A Passive Voltage-Balancing Method for Series-Connected SiC MOSFETs in Pulse Generator Based on Snubber Circuit. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Liang Yu, Wenjie Sun, Chenguo Yao, Shoulong Dong, Kai Li, Dazhao He, Yaobin Jin, Zongqing Bo |
A Novel Boost Marx Pulse Generator Based on Single-Driver Series-Connected SiC MOSFETs. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Qinghao Zhang, Pinjia Zhang |
A Junction Temperature Smoothing Control Method for SiC MOSFETs Based on the Gate Driving Signal Delay. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Oriol Avino-Salvado, Cyril Buttay, Ferran Bonet, Christophe Raynaud, Pascal Bevilacqua, José Rebollo, Hervé Morel, Xavier Perpiñà |
Physics-Based Strategies for Fast TDDB Testing and Lifetime Estimation in SiC Power MOSFETs. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Yanan Liu, Xinke Wu, Siliang Zhang |
A Simple Input Filter Capacitance (IFC) Current Compensation Scheme for CRM Totem-Pole PFC With Si MOSFETs at 800 Hz Line Frequency. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Minghang Xie, Pengju Sun, Wenyuan Ouyang, Quanming Luo, Xiong Du |
Online Monitoring Bond Wires Fault of SiC MOSFETs With Kelvin Package Based on Turn-on Source Voltage Ringing. |
IEEE Trans. Ind. Electron. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Xiaoqing Chen, Feng Li, Herbert Hess |
Design of Enhancement Mode β-Ga₂O₃ Vertical Current Aperture MOSFETs With a Trench Gate. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Sanket Parashar, Semih Isik, Nithin Kolli, Raj Kumar Kokkonda, Subhashish Bhattacharya |
Overvoltage Protection of Series-Connected 10kV SiC MOSFETs Following Switch Failures in MV 3L-NPC Converter for Safe Fault Isolation and Shutdown. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori |
Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs. |
IEEE Access |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Quan Nguyen-Gia, Hyungcheol Shin |
Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2024 |
DBLP DOI BibTeX RDF |
|
15 | Qinghao Zhang, Geye Lu, Yanyong Yang, Pinjia Zhang |
A High-Frequency Online Junction Temperature Monitoring Method for SiC mosfets Based on on-State Resistance With Aging Compensation. |
IEEE Trans. Ind. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Jianlong Kang, Qing Liu, Haoze Luo, Hu Cao, Zi-Hui Zhang, Zhen Xin |
Investigation of Off-State Stress Induced Degradation of SiC MOSFETs Under Short-Circuit Condition. |
IEEE Trans. Ind. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Qinghao Zhang, Pinjia Zhang |
A Novel Model of the Aging Effect on the ON-State Resistance of SiC Power MOSFETs for High-Accuracy Package-Related Aging Evaluation. |
IEEE Trans. Ind. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Rui Wang 0105, Asger Bjørn Jørgensen, Wentao Liu 0003, Hongbo Zhao 0004, Zhixing Yan, Stig Munk-Nielsen |
Voltage Balancing of Series-Connected SiC mosfets With Adaptive-Impedance Self-Powered Gate Drivers. |
IEEE Trans. Ind. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Chengmin Li, Jing Sheng, Drazen Dujic |
Reliable Gate Driving of SiC MOSFETs With Crosstalk Voltage Elimination and Two-Step Short-Circuit Protection. |
IEEE Trans. Ind. Electron. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka |
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. |
IEEE J. Solid State Circuits |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Hongwei Chen, Sheng Ai, Ziling Nie, Fengrui Cui, Pengfei Yuan |
Modulation Strategy for Suppressing Peak Voltage Spikes of SiC-MOSFETs During ANPC Commutation. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Pierpaolo Dini, Sergio Saponara, Sajib Chakraborty, Farzad Hosseinabadi, Omar Hegazy |
Experimental Characterization and Electro-Thermal Modeling of Double Side Cooled SiC MOSFETs for Accurate and Rapid Power Converter Simulations. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Vikas Joshi, Utkarsh Jadli, Peyush Pande, Mayank Chaturvedi, Daniel Haasmann, Sima Dimitrijev |
Circuit-Specific and Technology-Independent Criterion for Selection of Power MOSFETs That Minimize Energy Dissipation. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Siyoun Lee, Seong-Yeon Kim, Haesoon Oh, Jaesung Sim, Woo Young Choi |
Influence of Hole Current Crowding on Snapback Breakdown in Multi-Finger MOSFETs. |
IEEE Access |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Francesco Vecil, José Miguel Mantas, Pedro Alonso-Jordá |
Efficient GPU implementation of a Boltzmann-Schrödinger-Poisson solver for the simulation of nanoscale DG MOSFETs. |
J. Supercomput. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Franz Vollmaier, Thomas Langbauer, Klaus Krischan, Roberto Petrella |
The impact of DC-bus impedance on the switching performance of low-voltage silicon power MOSFETs. |
Elektrotech. Informationstechnik |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Jianwen Cao, Ze-kun Zhou, Yue Shi 0001, Bo Zhang 0031 |
An Integrated Gate Driver Based on SiC MOSFETs Adaptive Multi-Level Control Technique. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Guodong Qi, Xinyu Chen, Guangxi Hu, Peng Zhou, Wenzhong Bao, Ye Lu |
Knowledge-based neural network SPICE modeling for MOSFETs and its application on 2D material field-effect transistors. |
Sci. China Inf. Sci. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar |
Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xuejing Yang, Seungkyeong Lee, Songcheol Hong, Kyounghoon Yang |
Systematic characterization for RF small-signal parameter extraction of 28 nm FDSOI MOSFETs up to 110 GHz. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta |
Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | P. S. T. N. Srinivas, Satyabrata Jit, Pramod Kumar Tiwari |
Impact of self-heating on thermal noise in In1-xGaxAs GAA MOSFETs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Alok Kumar, Tarun Kumar Gupta, Bhavana P. Shrivastava, Abhinav Gupta |
Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xiaole Jia, Yibo Wang, Jinyu Yang, Yan Liu, Yue Hao, Genquan Han |
A compact model of DC I-V characteristics for depleted Ga2O3 MOSFETs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Xinfang Liao, Changqing Xu, Yi Liu 0060, Chen Wang, Dongdong Chen 0010, Yintang Yang |
Machine learning based prediction model for single event burnout hardening design of power MOSFETs. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Jialin Zheng, Zhengming Zhao, Han Xu, Weicheng Liu, Yangbin Zeng |
Accurate Time-segmented Loss Model for SiC MOSFETs in Electro-thermal Multi-Rate Simulation. |
CoRR |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Yingdong Wei, Chenyu Yao, Li Han, Libo Zhang, Zhiqingzi Chen, Lin Wang, Wei Lu, Xiaoshuang Chen |
The Microscopic Mechanisms of Nonlinear Rectification on Si-MOSFETs Terahertz Detector. |
Sensors |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Francesco Gagliardi 0002, Alessandro Catania, Andrea Ria, Paolo Bruschi, Massimo Piotto |
A Compact All-MOSFETs PVT-compensated Current Reference with Untrimmed 0.88%-(σ/μ). |
PRIME |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Sara Vecchi, Paolo Pavan, Francesco Maria Puglisi |
A Unified Framework to Explain Random Telegraph Noise Complexity in MOSFETs and RRAMs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Patrick Fiorenza, Francesco Cordiano, Mario Santo Alessandrino, Alfio Russo, Edoardo Zanetti, Mario Saggio, C. Bongiorno, Filippo Giannazzo, Fabrizio Roccaforte |
Consideration on the extrapolation of the low insulator field TDDB in 4H-SiC power MOSFETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | R. Green, A. Lelis, D. Urciuoli, E. Schroen, D. Habersat |
Dynamic On-State Resistance in SiC MOSFETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Elena Mengotti, Enea Bianda, David Baumann, Gerd Schlottig, Francisco Canales |
Industrial approach to the chip and package reliability of SiC MOSFETs (Invited). |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
|
15 | Shengnan Zhu, Limeng Shi, Michael Jin, Jiashu Qian, Monikuntala Bhattacharya, Hema Lata Rao Maddi, Marvin H. White, Anant K. Agarwal, Tianshi Liu, Atsushi Shimbori, Chingchi Chen |
Reliability Comparison of Commercial Planar and Trench 4H-SiC Power MOSFETs. |
IRPS |
2023 |
DBLP DOI BibTeX RDF |
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