Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
141 | Hui Min Wang, Chung-Len Lee 0001, Jwu E. Chen |
Factorization of Multi-Valued Logic Functions. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
multi-valued logic function factorization, multi valued logic functions, rectangular covering problem, MVL algebraic factorization algorithm, MVL Boolean properties, purely algebraic factorization algorithm, multilevel implementation, Boolean method, MVL example functions, computational complexity, complexity, Boolean functions, multivalued logic |
115 | Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar |
Technique of Computing Logic Derivatives for MVL-Functions. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
logic derivatives, partial direct, inverse derivatives, matrix approach, MVL switching circuit, truth vectors, multivalued logic, logic processing, MVL-functions |
110 | Svetlana N. Yanushkevich, Piotr Dziurzanski, Vlad P. Shmerko |
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model. |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
multiple-valued logic functions, linear word-level expressions, word-level decision diagrams |
110 | Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka |
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
|
94 | K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic |
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
|
94 | Zheng Tang, Okihiko Ishizuka, Koichi Tanno |
Learning Multiple-Valued Logic Networks Based on Back Propagation. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness |
94 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan |
New MVL-PLA Structures Based on Current-Mode CMOS Technology. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic |
80 | Michael S. Wills |
A behavioral model and triggering modes for MVL R-flops. |
MVL |
1978 |
DBLP BibTeX RDF |
|
73 | Tetsuro Ogi, Takuro Kayahara, Toshio Yamada, Michitaka Hirose |
MVL Toolkit: Software Library for Constructing an Immersive Shared Virtual World. |
VR |
2004 |
DBLP DOI BibTeX RDF |
|
73 | Arkadij Zakrevskij, Lev Zakrevski |
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions. |
ISMVL |
1997 |
DBLP DOI BibTeX RDF |
|
63 | Christian Lang 0001, Bernd Steinbach |
Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining. |
Artif. Intell. Rev. |
2003 |
DBLP DOI BibTeX RDF |
bi-decomposition, differential calculus, multi-level circuit design, data mining, machine learning, logic synthesis, multiple-valued logic |
63 | Liam P. Maguire, T. Martin McGinnity, L. J. McDaid |
From a Fuzzy Flip-Flop to a MVL Flip-Flop. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
MVL flip-flop, MOS implementation, fuzzy reasoning |
63 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid |
On the Synthesis of MVL Functions Using Input and Output Phase Assignments. |
ISMVL |
1997 |
DBLP DOI BibTeX RDF |
MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic |
63 | Elena Dubrova, Dilian Gurov, Jon C. Muzio |
The Evaluation of Full Sensitivity for Test Generation in MVL Circuits. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
full sensitivity evaluation, MVL circuits, functional level, m-valued n-variable functions, multi-valued logic circuits, fault diagnosis, logic testing, test generation, circuit analysis computing, multivalued logic circuits |
57 | Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif |
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
57 | Mitchell A. Thornton |
Spectral Transforms of Mixed-radix MVL Functions. |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
57 | Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic |
Generic Implementation of DD Packages in MVL. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
54 | |
Proceedings of the eighth international symposium on Multiple-valued logic, MVL 1978, Rosemont, Illinois, USA, 1978 |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | André Thayse, Marc Davio, Jean-Pierre Deschamps |
Optimization of multivalued decision algorithms. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Serge Perrine |
A new aspect of Some Post algebras. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Tatsuo Higuchi 0001, Hisamitsu Hoshi |
Special-purpose ternary computer for digital filtering. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | James R. Armstrong |
The modular complexity of a tree structured higher radix multiplier. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Steve Winker, Larry Wos |
Automated generation of models and counterexamples and its application to open questions in Ternary Boolean algebra. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Malcolm H. Steward |
The arithmetic properties of certain number systems. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Louis H. Kauffman |
De Morgan Algebras - completeness and recursion. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | George Epstein |
A summary of investigations into three and four valued logics. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | K. Wayne Current, Douglas A. Mow |
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Louise Martin, Corina Reischer, Ivo G. Rosenberg |
Completeness problems for switching circuits constructed from delayed gates. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Samuel C. Lee, Yousef M. Ajabnoor |
Digital calculus: ss. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Stanley J. Krolikoski |
A proposed interpretation of lukasiewicz's four-valued system of modal logic. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Marc Davio, Jean-Pierre Deschamps |
Addition in signed digit number systems. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Vason P. Srini |
Iterative realization of multivalued logic systems. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Abraham Kandel |
On the compactification and enumeration of distinct fuzzy switching functions. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Stephen C. Crist |
A tri-state logic family. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | James H. Pugsley, Charles B. Silio Jr. |
Some I2L circuits for multiple-valued logic. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Ytzhak H. Levendel, Melvin A. Breuer |
Vector representation of switching and three-valued functions. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Adit D. Singh, James R. Armstrong |
A simultaneous, radix four, I2L multiplier mechanized via repeated addition. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Luisa Iturrioz |
Two typical representation theorems for symmetrical Heyting algebras of order n. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Tsutomu Sasao |
An application of multiple-valued logic to a design of programmable logic arrays. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Tich T. Dao |
Design and implementation of a non-binary code for byte-organized memory with binary and quaternary logics. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Edward J. McCluskey |
Logic design of multi-valued I2L logic circuits. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | José Luis Huertas, José I. Acha, L. Macias |
On the synthesis of multivalued circuits using principally binary elements. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | K. Wayne Current, Douglas A. Mow |
Four-valued threshold logic full adder circuit implementations. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Masao Mukaidono |
The B-ternary logic and its applications to the detection of hazards in combinational switching circuits. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Daniel Etiemble |
TTL circuits for a 4-valued bus a way to reduce package and interconnections. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Ira Howard Sack |
Prefilters over an arbitrary Boolean Algebra. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Daniel E. Atkins |
A suggested approach to computer arithmetic for designers of multi-valued logic processors. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Majid A. H. Abdul-Karim, N. E. Berbat |
A simulataneous analog/ternary converter. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | David Rine |
Possibility theory: As a means for modeling computer security and protection. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Motinori Goto, Shinji Kao, Tomoko Ninomiya |
Determination of the fittest number of truth-values and canonical forms of logical functions for a many-valued axiom set by a computer. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Mark E. Stickel |
Fuzzy four-valued logic for inconsistency and uncertainty. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Jon C. Muzio, T. C. Wesselkamper |
Generalized finite Post algebras. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | James E. Smith, Jean-Pierre Dussault |
Fault secure multiple-valued logic networks. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | John R. Miller |
Use of an infinite-valued propositional calculus in a document retrieval system. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Ytzhak H. Levendel, Melvin A. Breuer |
Mathematical properties of Boolean transformations. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Majid A. H. Abdul-Karim |
A ternary J - K memory. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Claudio Moraga |
Complex spectral logic. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Jürgen Fricke |
Decomposition of multiple-valued logic functions. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | T. C. Yang, Anthony S. Wojcik |
Parallel and serial decompositions of multi-valued sequential machines. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | Ladislav J. Kohout |
Analysis of computing protection structures by means of multi-valued logic systems. |
MVL |
1978 |
DBLP BibTeX RDF |
|
54 | José Luis Huertas, José I. Acha, G. Sanchez Gomez |
Theory and design of multivalued memory elements. |
MVL |
1978 |
DBLP BibTeX RDF |
|
52 | Ugur Kalay, Marek A. Perkowski, Douglas V. Hall |
Highly Testable Boolean Ring Logic Circuits. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits |
52 | A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton |
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function |
52 | Zeljko Zilic, Zvonko G. Vranesic |
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
Reed-Muller forms, sparse polynomial interpolation, MVL RM transforms, interpolation, multivalued logic, Reed-Muller codes, polynomial interpolation, incompletely specified functions, computationally efficient algorithm |
52 | Arif Abdul Mannan, Koichi Tanno, Hiroki Tamura, Takako Toyama, Agung Darmawansyah |
Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator. |
ISMVL |
2013 |
DBLP DOI BibTeX RDF |
|
52 | Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire |
Re-Programmable MVL Circuits and Architecture to Enable Evolvable MVL Hardware. |
J. Multiple Valued Log. Soft Comput. |
2003 |
DBLP BibTeX RDF |
|
52 | Gerhard W. Dueck, D. Michael Miller |
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. |
ISMVL |
1990 |
DBLP DOI BibTeX RDF |
|
47 | Daniel H.-Y. Teng, Ronald J. Bolton |
Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. |
ISMVL |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic |
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
multiple-valued logic functions, information theory measures, decision trees, minimization |
47 | Mostafa I. H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman |
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Takao Waho |
Resonant Tunneling Transistor and Its Application to Multiple-Valued Logic Circuits. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
resonant tunnelling transistors, resonant tunneling transistors, multiple-valued logic circuits, multiple stable states, coupled-quantum-well, monostable-multistable logic circuits, multivalued logic circuits, resonant tunneling diodes, circuit stability |
47 | Craig M. Files, Rolf Drechsler, Marek A. Perkowski |
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. |
ISMVL |
1997 |
DBLP DOI BibTeX RDF |
learning samples, minterms, machine learning, learning (artificial intelligence), minimization, functional decomposition, multi-valued logic, multi-valued decision diagrams, problem complexity, MVL functions |
47 | Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky |
Algorithmic Synthesis of MVL Functions for CCD Implementation. |
IEEE Trans. Computers |
1991 |
DBLP DOI BibTeX RDF |
algorithmic synthesis, CCD implementation, sum of products, logic design, many-valued logics, logic circuits, charge-coupled devices, MVL functions, literals |
42 | Dan Olson, K. Wayne Current |
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
MVL Hardware, Ternary Addition, MVL Structure, SUS-LOC |
42 | Elena N. Zaitseva, Tatiana Kalganova, Evgeny G. Kochergov |
Logical Not Polynomial Forms to Represent Multiple-Valued Functions. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
logical not polynomial forms of MVL function, fast discrete orthogonal transform, genetic algorithms, MVL function |
37 | Omid Mirmotahari, Yngvar Berg |
Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
floating-gate (FG), multiple-valued logic (MVL), bidirectional |
37 | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
fixed polarity Reed-Muller expression, symmetric functions, MVL functions |
37 | Lutz J. Micheel, Hans L. Hartnagel |
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion |
31 | Mark H. Nodine, Craig M. Files |
A Mature Methodology for Implementing Multi-Valued Logic in Silicon. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
one-hot encoding, 1-of-N encoding, domino logic, null value |
31 | Silvia Gabrielli, Markus Hodapp, Roberto Ranon |
Designing a Multipurpose Virtual Laboratory to Support Communities of Practice in Physics. |
e-Science |
2006 |
DBLP DOI BibTeX RDF |
|
31 | M. S. Bhat 0001, H. S. Jamadagni |
Static power minimization in current-mode circuits. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
31 | M. S. Bhat 0001, H. S. Jamadagni |
Power Optimization in Current Mode Circuits. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim |
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hiroshi Inokawa, Yasuo Takahashi |
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. |
ISMVL |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko |
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model. |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
multiple-valued logic circuits, word-level decision diagrams |
31 | Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka |
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim |
Fault Analysis of the Multiple Valued Logic Using Spectral Method. |
ISMVL |
2000 |
DBLP DOI BibTeX RDF |
spectral domain, bridging fault, multiple valued logic, fault analysis |
31 | Gregory E. Beers, Lizy Kurian John |
Novel Memory Bus Driver/Receiver Architecture for Higher Throughput. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Zeljko Zilic, Zvonko G. Vranesic |
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
|
31 | Wenjun Wang, Claudio Moraga |
Design of Multivalued Circuits using Genetic Algorithms. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Shulin Zhao 0003, Shibo Huang, Mengting Niu, Lei Xu, Lifeng Xu |
iTTCA-MVL: A multi-view learning model based on physicochemical information and sequence statistical information for tumor T cell antigens identification. |
Comput. Biol. Medicine |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Jiale Chang, Yanhui Wang, Siya Mi, Yu Zhang 0004 |
MVL-Tra: Multi-view LFM signal source classification using Transformer. |
Comput. Electr. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
26 | D. Michael Miller, Gerhard W. Dueck |
Function translations and search-based transformation for MVL reversible circuit synthesis. |
Sci. Comput. Program. |
2021 |
DBLP DOI BibTeX RDF |
|
26 | D. Michael Miller, Gerhard W. Dueck |
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. |
ISMVL |
2021 |
DBLP DOI BibTeX RDF |
|
26 | T. Y. S. S. Santosh, Avirup Saha, Niloy Ganguly |
MVL: Multi-View Learning for News Recommendation. |
SIGIR |
2020 |
DBLP DOI BibTeX RDF |
|
26 | Mehdi Takbiri, Reza Faghih Mirzaee, Keivan Navi |
Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter. |
Circuits Syst. Signal Process. |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Ahmad Towhidy, Reza Omidi Gosheblagh, Karim Mohammadi |
An Efficient Current Mode MVL Residue Code Checker for Fault-Tolerant Arithmetic. |
J. Circuits Syst. Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Mahdieh Nayeri, Peiman Keshavarzian, Maryam Nayeri |
Approach for MVL design based on armchair graphene nanoribbon field effect transistor and arithmetic circuits design. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Yingchi Mao, Jianhua Zhang, Hai Qi, Longbao Wang |
DNN-MVL: DNN-Multi-View-Learning-Based Recover Block Missing Data in a Dam Safety Monitoring System. |
Sensors |
2019 |
DBLP DOI BibTeX RDF |
|
26 | Nils Przigoda, Judith Przigoda, Robert Wille |
Four-Valued Logic in UML/OCL Models: A "Playground" for the MVL Community. |
ISMVL |
2019 |
DBLP DOI BibTeX RDF |
|