Search results for "Manycore"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
66	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
66	Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus	NB-FEB: A Universal Scalable Easy-to-Use Synchronization Primitive for Manycore Architectures.	OPODIS	2009	DBLP DOI BibTeX RDF
66	Lin Huang 0002, Qiang Xu 0001	On Modeling the Lifetime Reliability of Homogeneous Manycore Systems.	PRDC	2008	DBLP DOI BibTeX RDF
58	Sachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou	Reinventing EDA with manycore processors.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, CAD, software, multicore, EDA, speedup, manycore
50	David A. Patterson 0001	Software knows best: portable parallelism requires standardized measurements of transparent hardware.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	standardized
50	Adam A. Porter, Victor Pankratius, Lawrence G. Votta	International workshop on multicore software engineering (IWMSE 2009).	ICSE Companion	2009	DBLP DOI BibTeX RDF
50	Victor Pankratius, Walter F. Tichy	International workshop on multicore software engineering (IWMSE 2008).	ICSE Companion	2008	DBLP DOI BibTeX RDF	concurrency, synchronization, static analysis, patterns, openmp, threads, cell, multicore systems, x10
49	Suzanne Rivoire	A breadth-first course in multicore and manycore programming.	SIGCSE	2010	DBLP DOI BibTeX RDF	multicore programming education, parallel programming education, tbb, openmp, cuda
49	Michael Boyer, David Tarjan, Scott T. Acton, Kevin Skadron	Accelerating leukocyte tracking using CUDA: A case study in leveraging manycore coprocessors.	IPDPS	2009	DBLP DOI BibTeX RDF
49	Nadathur Satish, Mark J. Harris, Michael Garland	Designing efficient sorting algorithms for manycore GPUs.	IPDPS	2009	DBLP DOI BibTeX RDF
49	Lei Zhang 0008, Yinhe Han 0001, Qiang Xu 0001, Xiaowei Li 0001	Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.	DATE	2008	DBLP DOI BibTeX RDF
49	Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin 0002, Hyunjin Lee, Kiyeon Lee, Michael Moeng	TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation.	ICPP	2008	DBLP DOI BibTeX RDF
41	Hun Jung, Miao Ju, Hao Che	A Theoretical Framework for Design Space Exploration of Manycore Processors.	MASCOTS	2011	DBLP DOI BibTeX RDF	CMP, multicore, design space exploration, queuing network, manycore
41	Pierre Michaud, Yiannakis Sazeides, André Seznec	Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	activity migration, sequential performance, power, multicore, temperature, cache misses, manycore
41	Amr M. Bayoumi, Yasser Y. Hanafy	Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures.	IFMT	2008	DBLP DOI BibTeX RDF	BSIM, parallel computing, graphics processing units, GPGPU, SIMD, SPICE, manycore
33	Victor Pankratius, Michael Philippsen	New Horizons in Multicore Software Engineering.	ICSE (2)	2010	DBLP DOI BibTeX RDF
33	Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic	RAMP gold: an FPGA-based architecture simulator for multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, FPGA, multiprocessors
33	John Nickolls, Ian Buck, Michael Garland, Kevin Skadron	Scalable Parallel Programming with CUDA.	ACM Queue	2008	DBLP DOI BibTeX RDF
33	Jike Chong, Nadathur Satish, Bryan Catanzaro, Kaushik Ravindran, Kurt Keutzer	Efficient Parallelization of H.264 Decoding with Macro Block Level Scheduling.	ICME	2007	DBLP DOI BibTeX RDF
33	Andrew A. Chien	Pervasive parallel computing: an historic opportunity for innovation in programming and architecture.	PPoPP	2007	DBLP DOI BibTeX RDF
32	Roberto R. Osorio, Javier D. Bruguera	An FPGA architecture for CABAC decoding in manycore systems.	ASAP	2008	DBLP DOI BibTeX RDF
32	Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic	Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
32	Michael Garland	Sparse matrix computations on manycore GPU's.	DAC	2008	DBLP DOI BibTeX RDF	parallel programming, GPU computing, shortest path algorithms, data-parallel algorithms, sparse matrix-vector multiplication
32	Xiaochun Ye, Van Hoa Nguyen, Dominique Lavenier, Dongrui Fan	Efficient Parallelization of a Protein Sequence Comparison Algorithm on Manycore Architecture.	PDCAT	2008	DBLP DOI BibTeX RDF
32	Sangyeun Cho, Lei Jin 0002, Kiyeon Lee	Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems.	RTCSA	2007	DBLP DOI BibTeX RDF
32	Pedro Henrique Penna	Nanvix : A Distributed Operating System for Lightweight Manycore Processors. (Nanvix : un système d'exploitation distribué pour les processeurs manycore légers).		2021	RDF
32	Hugo Taboada	Recouvrement des Collectives MPI Non-bloquantes sur Processeur Manycore. (MPI Non-Blocking Collective Overlap on Manycore Processor).		2018	RDF
32	Hoby Rakotoarivelo	Contributions au co-design de noyaux irréguliers sur architectures manycore: cas du remaillage anisotrope multi-échelle en mécanique des fluides numérique. (Contributions to the co-design of irregular kernels on manycore architectures: case of the anisotropic multi-scale mesh adaptation involved in computational fluid dynamics).		2018	RDF
32	Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan	Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
32	Clement Devigne	Exécution sécurisée de plusieurs machines virtuelles sur une plateforme Manycore. (Executing secured virtual machines within a Manycore architecture).		2017	RDF
32	Van Toan Dao	Calcul à haute performance et simulations stochastiques : Etude de la reproductibiité numérique sur architectures multicore et manycore. (High performance computing and stochastic simulation : Study of numerical reproducibility on multicore and manycore architectures).		2017	RDF
32	Hao Liu 0022	Protocoles scalables de cohérence des caches pour processeurs manycore à espace d'adressage partagé visant la basse consommation. (Scalable cache coherence protocols for energy-efficient shared memory manycore processors).		2016	RDF
32	Pierre Guillou	Compilation efficace d'applications de traitement d'images pour processeurs manycore. (Efficient Compilation of Image Processing Applications for Manycore Processors).		2016	RDF
32	Pierre Schweitzer	Simulations parallèles de Monte Carlo appliquées à la Physique des Hautes Energies pour plates-formes manycore et multicore : mise au point, optimisation, reproductibilité. (Monte Carlo parallel simulations applied to the High Energy Physics for manycore and multicore platforms : development, optimisation, reproducibility).		2015	RDF
32	Haruka Mori, Kenji Kise	Design and Performance Evaluation of a Manycore Processor for Large FPGA.	MCSoC	2014	DBLP DOI BibTeX RDF
32	Paraskevas Bourgos	Rigorous Design Flow for Programming Manycore Platforms. (Flot de conception rigoureux pour la programmation de plates-formes manycore.).		2013	RDF
25	Jonas Diemer, Rolf Ernst	Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks.	NOCS	2010	DBLP DOI BibTeX RDF	Latency-Sensitive, Quality of Service, QoS, Real-Time, NoC, Manycore
25	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
25	Oreste Villa, Gianluca Palermo, Cristina Silvano	Efficiency and scalability of barrier synchronization on NoC based many-core architectures.	CASES	2008	DBLP DOI BibTeX RDF	scalability, synchronization, efficiency, Multicore, NoC, barrier, Manycore
25	Bryan Catanzaro, Kurt Keutzer, Bor-Yiing Su	Parallelizing CAD: a timely research agenda for EDA.	DAC	2008	DBLP DOI BibTeX RDF	parallelization, framework, pattern, manycore
25	Jesse Z. Fang	Parallel programming environment: a key to translating tera-scale platforms into a big success.	PPoPP	2007	DBLP DOI BibTeX RDF	software tools, parallel programming models, manycore
17	John A. Stratton, Vinod Grover, Jaydeep Marathe, Bastiaan Aarts, Mike Murphy, Ziang Hu, Wen-mei W. Hwu	Efficient compilation of fine-grained SPMD-threaded programs for multicore CPUs.	CGO	2010	DBLP DOI BibTeX RDF	multicore, CUDA, CPU, SPMD
17	Victor Pankratius, Walter F. Tichy, Peter Hinsbeeck	Multicore software engineering: the next challenge in software engineering.	ICSE (2)	2010	DBLP DOI BibTeX RDF
17	Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
17	Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi	Best-effort semantic document search on GPUs.	GPGPU	2010	DBLP DOI BibTeX RDF	best-effort computing, dependency relaxation, supervised semantic indexing, GPGPU, CUDA, document search
17	Cor Meenderinck, Arnaldo Azevedo, Ben H. H. Juurlink, Mauricio Alvarez 0001, Alex Ramírez	Parallel Scalability of Video Decoders.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Scalability, Parallel processing, Chip multiprocessors, H.264, Video codecs
17	Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt	Analyzing CUDA workloads using a detailed GPU simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
17	David P. Luebke	Graphics hardware & GPU computing: past, present, and future.	Graphics Interface	2009	DBLP BibTeX RDF
17	David Tarjan, Jiayuan Meng, Kevin Skadron	Increasing memory miss tolerance for SIMD cores.	SC	2009	DBLP DOI BibTeX RDF
17	Michal Cernanský	Training Recurrent Neural Network Using Multistream Extended Kalman Filter on Multicore Processor and Cuda Enabled Graphic Processor Unit.	ICANN (1)	2009	DBLP DOI BibTeX RDF
17	Seunghwa Kang, David A. Bader	An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs.	PPoPP	2009	DBLP DOI BibTeX RDF	minimum spanning forest, transactional memory, minimum spanning tree
17	Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan	Larrabee: a many-core x86 architecture for visual computing.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, realtime graphics, software rendering, throughput computing, visual computing, parallel processing, GPGPU, SIMD
17	Carsten Trinitis, Martin Schulz 0001	7th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments: New Directions and Work-in-Progress (ParSim 2008).	PVM/MPI	2008	DBLP DOI BibTeX RDF
17	David P. Luebke	CUDA: Scalable parallel programming for high-performance scientific computing.	ISBI	2008	DBLP DOI BibTeX RDF
17	Michael Bader	Exploiting the Locality Properties of Peano Curves for Parallel Matrix Multiplication.	Euro-Par	2008	DBLP DOI BibTeX RDF
17	Matthew Fluet, Mike Rainey, John H. Reppy	A scheduling framework for general-purpose parallel languages.	ICFP	2008	DBLP DOI BibTeX RDF	heterogeneous parallel languages, scheduling, compilers, run-time systems
17	Reiner W. Hartenstein	The von Neumann Syndrome and the CS Education Dilemma.	ARC	2008	DBLP DOI BibTeX RDF
17	Joel R. Phillips, Kurt Keutzer, Michael Wrinn	Architecting parallel programs.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Tirath Ramdas, Gregory K. Egan, David Abramson 0001, Kim K. Baldridge	Run-time thread sorting to expose data-level parallelism.	ASAP	2008	DBLP DOI BibTeX RDF
17	Fei Wei, Huazhong Yang	Directed transmission method, a fully asynchronous approach to solve sparse linear systems in parallel.	SPAA	2008	DBLP DOI BibTeX RDF	convergence theory, directed transmission method (dtm), virtual transmission method (vtm), distributed algorithm, sparse linear system, asynchronous algorithm
17	Tim Mattson, Michael Wrinn	Parallel programming: can we PLEASE get it right this time?	DAC	2008	DBLP DOI BibTeX RDF	parallel computing, design patterns
17	Carsten Trinitis, Martin Schulz 0001	6th International Special Session on Current Trends in Numerical Simulation for Parallel Engineering Environments New Directions and Work-in-Progress ParSim 2007.	PVM/MPI	2007	DBLP DOI BibTeX RDF
17	Robert Schreiber	Manycores in the Future.	HPCC	2007	DBLP DOI BibTeX RDF
17	Jiulong Shan, Yurong Chen 0001, Qian Diao, Yimin Zhang 0002	Parallel Information Extraction on Shared Memory Multi-processor System.	ICPP	2006	DBLP DOI BibTeX RDF
17	John L. Gustafson	Reevaluating Amdahl's Law.	Commun. ACM	1988	DBLP DOI BibTeX RDF
16	Min Tian, Qi Liu, Jingshan Pan, Ying Gou, Zanjun Zhang	swPTS: an efficient parallel Thomas split algorithm for tridiagonal systems on Sunway manycore processors.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
16	Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini	LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation.	CoRR	2024	DBLP DOI BibTeX RDF
16	Sergio Mazzola, Samuel Riedel, Luca Benini	Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters.	CoRR	2024	DBLP DOI BibTeX RDF
16	Fatemeh Hossein Khani, Omid Akbari, Muhammad Shafique 0001	A Two-Level Thermal Cycling-aware Task Mapping Technique for Reliability Management in Manycore Systems.	CoRR	2024	DBLP DOI BibTeX RDF
16	Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande	Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads.	CoRR	2024	DBLP DOI BibTeX RDF
16	Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus	A 475 MHz Manycore FPGA Accelerator for RTL Simulation.	FPGA	2024	DBLP DOI BibTeX RDF
16	Jan Finkbeiner, Thomas Gmeinder, Mark Pupilli, Alexander Titterton, Emre Neftci	Harnessing Manycore Processors with Distributed Memory for Accelerated Training of Sparse and Recurrent Models.	AAAI	2024	DBLP DOI BibTeX RDF
16	João Fellipe Uller, João Vicente Souto, Pedro Henrique Penna, Márcio Castro 0001, Henrique Cota de Freitas, Jean-François Méhaut	LWMPI: An MPI library for NoC-based lightweight manycore processors with on-chip memory constraints.	Concurr. Comput. Pract. Exp.	2023	DBLP DOI BibTeX RDF
16	Ramesh Sambangi, Arun Sammit Pandey, Kanchan Manna, Sudipta Mahapatra, Santanu Chattopadhyay	Application Mapping Onto Manycore Processor Architectures Using Active Search Framework.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini	MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
16	Xin Li 0042, Zhi Li, Yaqi Ju, Xiaofei Zhang, Rongyao Wang, Wei Zhou 0020	COP: A Combinational Optimization Power Budgeting Method for Manycore Systems in Dark Silicon.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
16	Gaurav Narang, Aryan Deshwal, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande	Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
16	Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini	MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory.	CoRR	2023	DBLP DOI BibTeX RDF
16	Jan Finkbeiner, Thomas Gmeinder, Mark Pupilli, Alexander Titterton, Emre Neftci	Harnessing Manycore Processors with Distributed Memory for Accelerated Training of Sparse and Recurrent Models.	CoRR	2023	DBLP DOI BibTeX RDF
16	Ali Shoker, Paulo Esteves Veríssimo, Marcus Völp	The Path to Fault- and Intrusion-Resilient Manycore Systems on a Chip.	CoRR	2023	DBLP DOI BibTeX RDF
16	Haoran Lin, Lifeng Yan, Qixin Chang, Haitian Lu, Chenlin Li, Quanjie He, Zeyu Song, Xiaohui Duan, Zekun Yin, Yuxuan Li, Zhao Liu, Wei Xue, Haohuan Fu, Lin Gan, Guangwen Yang, Weiguo Liu	O2ATH: An OpenMP Offloading Toolkit for the Sunway Heterogeneous Manycore Platform.	CoRR	2023	DBLP DOI BibTeX RDF
16	Sirui Qi, Yingheng Li, Sudeep Pasricha, Ryan Gary Kim	MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms.	CoRR	2023	DBLP DOI BibTeX RDF
16	Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff	Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems.	CoRR	2023	DBLP DOI BibTeX RDF
16	Abeer Shdefat, Saad Bani-Mohammad, Ismail Ababneh	On Allocation Algorithms for Manycore Systems With Network on Chip.	Int. J. Grid High Perform. Comput.	2023	DBLP DOI BibTeX RDF
16	Mitsuhisa Sato, Miwako Tsuji	OpenACC Execution Models for Manycore Processor with ARM SVE.	HPC Asia Workshops	2023	DBLP DOI BibTeX RDF
16	Ali Shoker, Paulo Esteves Veríssimo, Marcus Völp	The Path to Fault- and Intrusion-Resilient Manycore Systems on a Chip.	DSN-S	2023	DBLP DOI BibTeX RDF
16	Harsh Sharma, Sumit K. Mandal, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande	Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures.	DATE	2023	DBLP DOI BibTeX RDF
16	Sirui Qi, Yingheng Li, Sudeep Pasricha, Ryan Gary Kim	MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore Platforms.	DATE	2023	DBLP DOI BibTeX RDF
16	Fei Gao 0016, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu 0001, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff	DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.	CICC	2023	DBLP DOI BibTeX RDF
16	Gaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande	Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems.	ISLPED	2023	DBLP DOI BibTeX RDF
16	Fabian Lesniak, Nidhi Anantharajaiah, Tanja Harbaum, Jürgen Becker 0001	Non-Intrusive Runtime Monitoring for Manycore Prototypes.	DroneSE/RAPIDO@HiPEAC	2023	DBLP DOI BibTeX RDF
16	Yoshiki Kawanishi, Patrick Finnerty, Tomio Kamada, Chikara Ohta	Distributed Cell Set : A Library for Space-Dependent Communication/Computation Overlap on Manycore Cluster.	PMAM@PPoPP	2023	DBLP DOI BibTeX RDF
16	Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Mark Oskin, Christopher Batten	Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories.	ASPLOS (3)	2023	DBLP DOI BibTeX RDF
16	Yuxuan Liu, Tianqiang Xu, Zeyu Mi, Zhichao Hua 0001, Binyu Zang, Haibo Chen 0001	CPS: A Cooperative Para-virtualized Scheduling Framework for Manycore Machines.	ASPLOS (4)	2023	DBLP DOI BibTeX RDF
16	Philipp Gypser	Mechanisms for energy-efficient processor allocation and redistribution on manycore systems.		2023	RDF
16	Eric T. Phipps, Roger P. Pawlowski, Christian Trott	Automatic Differentiation of C++ Codes on Emerging Manycore Architectures with Sacado.	ACM Trans. Math. Softw.	2022	DBLP DOI BibTeX RDF
16	Abdul Salam, Safdar Jamil, Sungwon Jung, Sung-Soon Park 0001, Youngjae Kim 0001	Future-Based Persistent Spatial Data Structure for NVM-Based Manycore Machines.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Min Tian, Junjie Wang, Zanjun Zhang, Wei Du, Jingshan Pan, Tao Liu 0029	swSuperLU: A highly scalable sparse direct solver on Sunway manycore architecture.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
16	Chawki Benchehida, Mohammed Kamel Benhaoua, Houssam-Eddine Zahaf, Giuseppe Lipari	Memory-processor co-scheduling for real-time tasks on network-on-chip manycore architectures.	Int. J. High Perform. Syst. Archit.	2022	DBLP DOI BibTeX RDF