Search results for "MediaBench"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith	MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems.	MICRO	1997	DBLP DOI BibTeX RDF	MediaBench, SPEC benchmark suite, benchmark suite, compilation technology, experimental measurement, general-purpose computing, general-purpose systems, inner-loops, optimization, multimedia systems, instruction-level parallelism, SIMD, VLIW, communications systems, embedded applications, microprocessor architectures
42	Jason E. Fritts, Frederick W. Steiling, Joseph A. Tucek, Wayne H. Wolf	MediaBench II video: Expediting the next generation of video systems research.	Microprocess. Microsystems	2009	DBLP DOI BibTeX RDF
25	Gokhan Memik, William H. Mangione-Smith	Evaluating Network Processors using NetBench.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Embedded systems, benchmarking, network processors
25	Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo	2D-VLIW: An Architecture Based on the Geometry of Computation.	ASAP	2006	DBLP DOI BibTeX RDF
25	Jiangjiang Liu 0002, Brian Bell, Tan Truong	Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
25	David M. Brooks, Margaret Martonosi	Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance.	ACM Trans. Comput. Syst.	2000	DBLP DOI BibTeX RDF
25	David M. Brooks, Margaret Martonosi	Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.	HPCA	1999	DBLP DOI BibTeX RDF
12	Silvian Calman, Jianwen Zhu	Interprocedural induction variable analysis based on interprocedural SSA form IR.	PASTE	2010	DBLP DOI BibTeX RDF	induction variable analysis, interprocedural ssa, ssa
12	Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran	SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.	DAC	2010	DBLP DOI BibTeX RDF	miss rate, simulation, round robin, cache simulation, L1 cache
12	Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere	Linux Kernel Compaction through Cold Code Swapping.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
12	Lian Li 0002, Hui Feng, Jingling Xue	Compiler-directed scratchpad memory management via graph coloring.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	live range splitting, memory coloring, graph coloring, memory allocation, Scratchpad memory, register coalescing, software-managed cache
12	Tyrel Russell, Abid M. Malik, Michael Chase, Peter van Beek	Learning Heuristics for the Superblock Instruction Scheduling Problem.	IEEE Trans. Knowl. Data Eng.	2009	DBLP DOI BibTeX RDF
12	Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Predictability, Multiprocessor, Compositionality, Cache management
12	Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot	Constraint-Driven Identification of Application Specific Instructions in the DURASE System.	SAMOS	2009	DBLP DOI BibTeX RDF
12	Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby	On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors.	HPCC	2009	DBLP DOI BibTeX RDF
12	Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
12	Silvian Calman, Jianwen Zhu	Increasing the Scope and Resolution of Interprocedural Static Single Assignment.	SAS	2009	DBLP DOI BibTeX RDF	dataflow, constant propagation, SSA, interprocedural
12	Kapil Anand, Rajeev Barua	Instruction cache locking inside a binary rewriter.	CASES	2009	DBLP DOI BibTeX RDF	cache locking, embedded systems, caches, binary rewriting
12	Jie Tao 0001, Dominic Hillenbrand, Holger Marten	Instruction Hints for Super Efficient Data Caches.	ICCS (2)	2009	DBLP DOI BibTeX RDF	simulation, architecture design, Cache optimization
12	Ozcan Ozturk 0001, Mahmut T. Kandemir, Guangyu Chen	Access pattern-based code compression for memory-constrained systems.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	CFG, code access pattern, Embedded systems, code compression, memory optimization
12	Shu Xiao 0001, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
12	Sanghyun Park, Aviral Shrivastava, Yunheung Paek	Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.	DATE	2008	DBLP DOI BibTeX RDF
12	Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana	Compositional, dynamic cache management for embedded chip multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
12	Mattias V. Eriksson, Oskar Skoog, Christoph W. Kessler	Optimal vs. heuristic integrated code generation for clustered VLIW architectures.	SCOPES	2008	DBLP DOI BibTeX RDF
12	Kenneth Hoste, Lieven Eeckhout	Characterizing the Unique and Diverse Behaviors in Existing and Emerging General-Purpose and Domain-Specific Benchmark Suites.	ISPASS	2008	DBLP DOI BibTeX RDF
12	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
12	Talal Bonny, Jörg Henkel	FBT: filled buffer technique to reduce code size for VLIW processors.	ICCAD	2008	DBLP DOI BibTeX RDF
12	Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau	Control flow optimization in loops using interval analysis.	CASES	2008	DBLP DOI BibTeX RDF	algorithmic code transformation, compiler loop optimization, interval analysis
12	Arun Rangasamy, Rahul Nagpal, Y. N. Srikant	Compiler-directed frequency and voltage scaling for a multiple clock domain microarchitecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	dvs, dynamic energy, energy, multiple clock domains
12	Allen C. Cheng	Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform.	ISQED	2008	DBLP DOI BibTeX RDF
12	Shlomit S. Pinter, Israel Waldman	Selective Code Compression Scheme for Embedded Systems.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	run-time decompression, Code compression, code size reduction
12	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail	Thermal Management of On-Chip Caches Through Power Density Minimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Shao-Yang Wang, Rong-Guey Chang	Code size reduction by compressing repeated instruction sequences.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching
12	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
12	Shu Xiao 0001, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
12	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh	Static strands: Safely exposing dependence chains for increasing embedded power efficiency.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	dependency collapsing, Architecture, energy, sequentiality
12	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach.	PACT	2007	DBLP DOI BibTeX RDF
12	Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim	DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems.	DATE	2007	DBLP DOI BibTeX RDF
12	Seok-Won Seong, Prabhat Mishra 0001	An efficient code compression technique using application-aware bitmask and dictionary selection methods.	DATE	2007	DBLP DOI BibTeX RDF
12	Yee Jern Chong, Sri Parameswaran	Automatic application specific floating-point unit generation.	DATE	2007	DBLP DOI BibTeX RDF
12	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel	Instruction trace compression for rapid instruction cache simulation.	DATE	2007	DBLP DOI BibTeX RDF
12	Josep M. Codina, F. Jesús Sánchez, Antonio González 0001	Virtual Cluster Scheduling Through the Scheduling Graph.	CGO	2007	DBLP DOI BibTeX RDF
12	Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau	Short-Circuit Compiler Transformation: Optimizing Conditional Blocks.	ASP-DAC	2007	DBLP DOI BibTeX RDF
12	Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001	NISD: A Framework for Automatic Narrow Instruction Set Design.	ICESS	2007	DBLP DOI BibTeX RDF	dual-width instruction set, narrow instruction set design, automatic instruction set design
12	Seunghoon Kim, Robert P. Dick, Russ Joseph	Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	power regulation, multimedia, chip multiprocessor, battery
12	Haifeng He, Saumya K. Debray, Gregory R. Andrews	The revenge of the overlay: automatic compaction of OS kernel code via on-demand code loading.	EMSOFT	2007	DBLP DOI BibTeX RDF	code clustering, embedded systems, code compaction, binary rewriting
12	Je-Hyung Lee, Jinpyo Park, Soo-Mook Moon	Securing More Registers with Reduced Instruction Encoding Architectures.	RTCSA	2007	DBLP DOI BibTeX RDF
12	Lian Li 0002, Hui Wu 0001, Hui Feng, Jingling Xue	Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
12	Philip Brisk, Ajay Kumar Verma, Paolo Ienne	An optimistic and conservative register assignment heuristic for chordal graphs.	CASES	2007	DBLP DOI BibTeX RDF	static single assignment (ssa) form, chordal graph, register assignment
12	André Silva, Guilherme Álvaro R. M. Esmeraldo, Edna Barros, Pablo Viana	Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
12	Kimish Patel, Wonbok Lee, Massoud Pedram	Minimizing power dissipation during write operation to register files.	ISLPED	2007	DBLP DOI BibTeX RDF	write operation, power, register file
12	Christophe Wolinski, Krzysztof Kuchcinski	Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints.	ASAP	2007	DBLP DOI BibTeX RDF
12	Eduardo Braulio Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet	A Code Compression Method to Cope with Security Hardware Overheads.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
12	Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda	Power Reduction in VLIW Processor with Compiler Driven Bypass Network.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
12	Soheil Ghiasi, Po-Kuan Huang, Roozbeh Jafari	Probabilistic delay budget assignment for synthesis of soft real-time applications.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel	Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
12	Ajay Joshi, Aashish Phansalkar, Lieven Eeckhout, Lizy Kurian John	Measuring Benchmark Similarity Using Inherent Program Characteristics.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	modeling techniques, performance of systems, Measurement techniques, performance attributes
12	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Power analysis
12	Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers	Offset assignment using simultaneous variable coalescing.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation
12	Kashif Ali, Mokhtar Aboelaze, Suprakash Datta	Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
12	Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff	Code Size Reduction by Compiler Tuning.	SAMOS	2006	DBLP DOI BibTeX RDF
12	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	A novel instruction scratchpad memory optimization method based on concomitance metric.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran	Finding optimal L1 cache configuration for embedded systems.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Yen-Jen Chang	Lazy BTB: reduce BTB energy consumption using dynamic profiling.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck	Instruction Transfer And Storage Exploration for Low Energy VLIWs.	SiPS	2006	DBLP DOI BibTeX RDF
12	Lian Li 0002, Jingling Xue	Trace-Based Data Cache Leakage Reduction at Link Time.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
12	John Gilbert, David M. Abrahamson	Adaptive object code compression.	CASES	2006	DBLP DOI BibTeX RDF	code compression, code size reduction, code compaction
12	Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar	Rapid Resource-Constrained Hardware Performance Estimation.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
12	Wonbok Lee, Kimish Patel, Massoud Pedram	Dynamic thermal management for MPEG-2 decoding.	ISLPED	2006	DBLP DOI BibTeX RDF	MPEG-2 decoding, thermal model, temperature-aware design
12	Israel Waldman, Shlomit S. Pinter	Profile-driven compression scheme for embedded systems.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	run-time decompression, code compression, code size reduction
12	Constantino G. Ribeiro, Marcelo Cintra	Quantifying Uncertainty in Points-To Relations.	LCPC	2006	DBLP DOI BibTeX RDF
12	Ajay Joshi, Lieven Eeckhout, Robert H. Bell Jr., Lizy Kurian John	Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks.	IISWC	2006	DBLP DOI BibTeX RDF
12	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail	Power density minimization for highly-associative caches in embedded processors.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	cache, embedded processor, leakage power, temperature
12	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	sequential access buffer, media benchmark, flexible sequential and random access memory, on-chip memory
12	Enric Gibert, F. Jesús Sánchez, Antonio González 0001	Distributed Data Cache Designs for Clustered VLIW Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	design styles, Single data stream architectures
12	Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo	Efficient datapath merging for partially reconfigurable architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Ankur Srivastava 0001, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh	On effective slack management in postscheduling phase.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Chuanjun Zhang, Frank Vahid, Jun Yang 0002, Walid A. Najjar	A way-halting cache for low-energy high-performance systems.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, dynamic optimization, low energy
12	Chuanjun Zhang, Frank Vahid, Walid A. Najjar	A highly configurable cache for low energy embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, low power, Cache, microprocessor, configurable, memory hierarchy, low energy, architecture tuning
12	Philip Brisk, Jamie Macbeth 0001, Ani Nahapetian, Majid Sarrafzadeh	A dictionary construction technique for code compression systems with echo instructions.	LCTES	2005	DBLP DOI BibTeX RDF	(dictionary) compression, echo instructions, scheduling
12	Peter G. Sassone, D. Scott Wills, Gabriel H. Loh	Static strands: safely collapsing dependence chains for increasing embedded power efficiency.	LCTES	2005	DBLP DOI BibTeX RDF	dependency collapsing, architecture, embedded, energy, sequentiality
12	Enric Gibert, Jaume Abella 0001, F. Jesús Sánchez, Xavier Vera, Antonio González 0001	Variable-Based Multi-module Data Caches for Clustered VLIW Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
12	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
12	Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne	ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.	DATE	2005	DBLP DOI BibTeX RDF
12	Tingting Sha, Milo M. K. Martin, Amir Roth	Scalable Store-Load Forwarding via Store Queue Index Prediction.	MICRO	2005	DBLP DOI BibTeX RDF
12	Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark	Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors.	HPCA	2005	DBLP DOI BibTeX RDF
12	Azadeh Davoodi, Ankur Srivastava 0001	Simultaneous floorplanning and resource binding: a probabilistic approach.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Kiruthika Selvamani, Tarek M. Taha	Estimating critical region parallelism to guide platform retargeting.	ACM Southeast Regional Conference (1)	2005	DBLP DOI BibTeX RDF	analytical model, performance prediction
12	Juan Chen 0001, Yong Dong, Huizhan Yi, Xuejun Yang	Power Consumption Analysis of Embedded Multimedia Application.	ICESS	2005	DBLP DOI BibTeX RDF
12	Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto	Design of a decompressor engine on a SPARC processor.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, code compression
12	Hongkyu Kim, D. Scott Wills, Linda M. Wills	Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
12	Trevor N. Mudge	Performance and power analysis of computer systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF
12	Kugan Vivekanandarajah, Thambipillai Srikanthan	Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
12	Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik	Load elimination for low-power embedded processors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	load elimination technique, low power design
12	Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta	Continuous Optimization.	ISCA	2005	DBLP DOI BibTeX RDF
12	Vlad Petric, Tingting Sha, Amir Roth	RENO - A Rename-Based Instruction Optimizer.	ISCA	2005	DBLP DOI BibTeX RDF
12	Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak	Flexible ASIC: shared masking for multiple media processors.	DAC	2005	DBLP DOI BibTeX RDF	optimization, interconnect, ASIC