Search results for "Memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	Chuan Yue, Richard Tran Mills, Andreas Stathopoulos, Dimitrios S. Nikolopoulos	Runtime Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory.	HPDC	2006	DBLP DOI BibTeX RDF	memory server, memory adaptation, local disk memory, remote memory capability, shared computational resource, network memory, memory malleability, MPI communication, cache memory, scientific application, virtual memory system
61	Chen Ding 0001, Chengliang Zhang, Xipeng Shen, Mitsunori Ogihara	Gated memory control for memory monitoring, leak detection and garbage collection.	Memory System Performance	2005	DBLP DOI BibTeX RDF	memory usage monitoring, object life, preventive memory management, memory leak, program phase
58	Justin Teller, Charles B. Silio Jr., Bruce L. Jacob	Performance characteristics of MAUI: an intelligent memory system architecture.	Memory System Performance	2005	DBLP DOI BibTeX RDF	MAUI memory architecture, SimpleScalar simulator, data-intensive calculations, intelligent memory, memory architecture, vector processing, SIMD processing
57	Gertrud S. Joachim	Memory Efficiency.	J. ACM	1959	DBLP DOI BibTeX RDF
56	Masato Oguchi, Hitoshi Aida, Tadao Saito	A Proposal for a DSM Architecture Suitable for a Widely Distributed Environment and its Evaluation.	HPDC	1995	DBLP DOI BibTeX RDF	distributed shared memory architecture, widely distributed environment, functionally distributed computing, software programming, replicated shared memory, internal machine memory, SPARCstations, SCRAMNet, latency hiding techniques, performance evaluation, parallel architectures, shared memory systems, distributed memory systems, data prefetching, multi-thread programming, shared virtual memory
56	John G. Cleary, Murray Pearson, Husam Kinawi	The architecture of an optimistic CPU: the WarpEngine.	HICSS (1)	1995	DBLP DOI BibTeX RDF	optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory
51	Mojtaba Mehrara, Todd M. Austin	Reliability-aware data placement for partial memory protection in embedded processors.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF	memory lifetime, partial memory protection, selective data placement, embedded systems, soft errors
51	Richard Tran Mills, Chuan Yue, Andreas Stathopoulos, Dimitrios S. Nikolopoulos	Runtime and Programming Support for Memory Adaptation in Scientific Applications via Local Disk and Remote Memory.	J. Grid Comput.	2007	DBLP DOI BibTeX RDF	Shared computational pools, Network RAM, Scientific libraries, Autonomic computing, Memory management
50	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	The Role of Associative Memory in Virtual Shared Memory Architectures: A Price-Performance Comparison.	PDP	1996	DBLP DOI BibTeX RDF	virtual shared memory architectures, price-performance, set associative memory, large coherent cache, performance evaluation, benchmarks, parallel machines, memory hierarchy, shared memory systems, costing, cost, associative memory, memory architecture, content-addressable storage, application specific, virtual storage, CC-NUMA, COMA, miss ratios
49	Sajal K. Das 0001, Sanjoy K. Sen	Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories.	IPPS	1996	DBLP DOI BibTeX RDF	buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time
49	Peter S. Magnusson, Bengt Werner	Efficient memory simulation in SimICS.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	efficient memory simulation, SimICS, instruction level simulator, complex memory hierarchies, user level code, system level code, software caching mechanism, Simulator Translation Cache, STC, interpreted memory operations, complex memory simulation code, lazy storage allocation, well defined internal interface, generic memory simulation, user extensions, threaded code, runtime selection, statistics gathering, memory profiling, data structures, data structures, virtual machines, multiprocessors, storage management, storage allocation
48	Kevin T. Lim, Jichuan Chang, Trevor N. Mudge, Parthasarathy Ranganathan, Steven K. Reinhardt, Thomas F. Wenisch	Disaggregated memory for expansion and sharing in blade servers.	ISCA	2009	DBLP DOI BibTeX RDF	disaggregated memory, memory blades, memory capacity expansion, power and cost efficiencies
48	Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark A. Heinrich	Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads.	ISPASS	2007	DBLP DOI BibTeX RDF	active memory cluster, directory protocol thread, active memory address remapping, parallel reduction, coherence protocol extension, software protocol, multi-threaded node, dual-core node, active memory architecture, distributed shared memory, multiprocessor architecture, memory controller, matrix transpose
48	Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins	Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	dynamic data types, multimedia, low power, memory management, memory hierarchy, memory bandwidth, dynamic memory management, system-level exploration, memory footprint
48	Wei Zhao, Christos A. Papachristou	Architectural partitioning of control memory for application specific programmable processors.	ICCAD	1995	DBLP DOI BibTeX RDF	application specific programmable processors, control memory, distributed microcode memory model, microcode memory, repetitive microcodes, distributed memory systems, memory architecture, programmability, microprogram, datapaths, firmware, memory module
47	Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatani	Instruction combining for coalescing memory accesses using global code motion.	Memory System Performance	2004	DBLP DOI BibTeX RDF	instruction combining, memory access coalescing, Java, JIT compilers, IA-64, 64-bit architectures
47	Ross McIlroy, Peter Dickman, Joe Sventek	Efficient dynamic heap allocation of scratch-pad memory.	ISMM	2008	DBLP DOI BibTeX RDF	on-core memory, concurrency, memory management
47	Betty Prince	Embedded non-volatile memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM
46	Xiaogang Qiu, Michel Dubois 0001	Tolerating Late Memory Traps in Dynamically Scheduled Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
46	Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Memory System Support for Image Processing.	IEEE PACT	1999	DBLP DOI BibTeX RDF	bus utilization, image processing, virtual memory, memory architecture, memory bandwidth, memory latency, cache efficiency
46	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Aggressive Memory-Aware Compilation.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
46	Mary W. Hall, Craig S. Steele	Memory Management in a PIM-Based Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
46	Yi Feng, Emery D. Berger	A locality-improving dynamic memory allocator.	Memory System Performance	2005	DBLP DOI BibTeX RDF	vam, memory management, virtual memory, paging, fragmentation, allocator, cache locality
44	Bülent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, T. Basil Smith	Hardware Compressed Main Memory: Operating System Support and Performance Evaluation.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Memory compression, memory and cache performance, webserver performance, memory management
44	Feng Qin, Shan Lu 0001, Yuanyuan Zhou 0001	SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs.	HPCA	2005	DBLP DOI BibTeX RDF
44	Gary S. Tyson, Todd M. Austin	Improving the Accuracy and Performance of Memory Communication Through Renaming.	MICRO	1997	DBLP DOI BibTeX RDF	data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation
44	Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde	Reflective-memory multiprocessor.	HICSS (1)	1995	DBLP DOI BibTeX RDF	reflective-memory multiprocessor, hardware-supported data replication, multiple computers, memory semantics, reflective memory implementation, Encore Infinity, spinlocks, cache coherency problems, massive replication, recovery procedure, crashed nodes, reliability, fault tolerant computing, shared memory systems, distributed memory systems, system recovery, cache storage, cached architectures, distributed shared memory multiprocessor
43	Mark S. Ackerman, Eric Mandel	Memory in the small: an application to provide task-based organizational memory for a scientific community .	HICSS (4)	1995	DBLP DOI BibTeX RDF	astronomy computing, scientific community, performance support mechanism, memory-in-the-small, astrophysicists, knowledge based systems, memory architecture, organizational memory, task performance, ASSIST
43	Easwaran Raman, David I. August	Recursive data structure profiling.	Memory System Performance	2005	DBLP DOI BibTeX RDF	RDS, dynamic shape graph, list linearization, memory profiling, shape profiling
43	Leonidas I. Kontothanassis, Michael L. Scott	Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory.	HPCA	1996	DBLP DOI BibTeX RDF	memory-mapped network interfaces, cache fills, fine-grain access faults, parallel algorithms, protocols, message passing, latency, bandwidth, shared memory systems, distributed shared memory, distributed memory systems, network interfaces, network interfaces, memory-mapped
43	Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron	Memory-miser: a performance-constrained runtime system for power-scalable clusters.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	resource allocation, control, power management, memory
42	Jeonghun Cho, Yunheung Paek	Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm.	EUC Workshops	2006	DBLP DOI BibTeX RDF	dual data memory banks, compiler and on-chip memory, DSP, Run-time environment
42	Ke Ning, David R. Kaeli	External memory page remapping for embedded multimedia systems.	LCTES	2007	DBLP DOI BibTeX RDF	memory coloring, memory page remapping, embedded systems, memory controllers
42	Thomas Stricker, Thomas R. Gross	Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems.	HPCA	1997	DBLP DOI BibTeX RDF	nonuniform bandwidth, memory system performance characterization, local memory accesses, remote write, cost benefit model, DEC Alpha based parallel systems, DEC-Alpha processor architecture, DEC 8400, scalability, compiler, parallel systems, empirical evaluation, memory architecture, coherency, cache storage, access pattern, spatial locality, local memory, global address space, Cray T3E, Cray T3D, clock speed
42	Milan M. Jovanovic, Milo Tomasevic, Veljko M. Milutinovic	A simulation-based comparison of two reflective memory approaches.	HICSS (1)	1995	DBLP DOI BibTeX RDF	simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data
42	Kunal Agrawal, Charles E. Leiserson, Jim Sukha	Memory models for open-nested transactions.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
42	Kartik Sudeep, Ahmed Gheith	Application analysis using memory pressure.	Memory System Performance	2005	DBLP DOI BibTeX RDF
42	Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku	Software Controlled Reconfigurable On-Chip Memory for High Performance Computing.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
41	Sze Wei Lee, Soon-Chieh Lim	An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	2-D DWT processing systems, memory mapping scheme, memeory access, memory bandwidth
41	Chitra Natarajan, Bruce Christenson, Faye A. Briggs	A study of performance impact of memory controller features in multi-processor server environment.	WMPI	2004	DBLP DOI BibTeX RDF	memory transaction scheduling, server systems, multi-processors, memory controller, memory subsystem, performance impact
41	Robert Cooksey, Dennis Colarelli, Dirk Grunwald	Content-Based Prefetching: Initial Results.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
41	Samir Ranjan Das, Richard Fujimoto	An Empirical Evaluation of Performance-Memory Trade-Offs in Time Warp.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	performance evaluation, Discrete event simulation, memory management, checkpointing, Time Warp, rollback, parallel and distributed simulation, virtual time
41	Matthew Hertz, Emery D. Berger	Quantifying the performance of garbage collection vs. explicit memory management.	OOPSLA	2005	DBLP DOI BibTeX RDF	explicit memory management, oracular memory management, performance analysis, throughput, garbage collection, paging, time-space tradeoff
41	Mohamed Shalan, Vincent John Mooney III	Hardware support for real-time embedded multiprocessor system-on-a-chip memory management.	CODES	2002	DBLP DOI BibTeX RDF	Atalanta, SoCDMMU, real-time operating systems., two-level memory management, real-time systems, embedded systems, System-on-a-Chip, dynamic memory management
40	Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An	A Scalable Memory System Design.	VLSI Design	1997	DBLP DOI BibTeX RDF	scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed
40	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
40	Dae Wook Bang, Yoo Kun Cho	Distributed shared memory for function-grained graph reduction machine.	PDP	1995	DBLP DOI BibTeX RDF	function-grained graph reduction machine, efficient DSM system, virtual global memory, function grained graph reduction machine, graph nodes, function applications, global memory access system, distributed graph nodes, H-object, memory coherence problem, weak coherence semantics, read operations, transputer network system, graph theory, resource allocation, parallel machines, parallel machine, distributed shared memory, distributed memory systems, processing elements, virtual storage, transputer systems
40	Ian Watson, Alasdair Rawsthorne	Decoupled pre-fetching for distributed shared memory.	HICSS (1)	1995	DBLP DOI BibTeX RDF	partial evaluation (compilers), distributed shared memory environment, decoupled pre-fetching, global view, remote memory copies, user annotations, compile-time analysis, run-time prediction, irregular access patterns, dual processor structure, partial program evaluation, data fetches, parallel architectures, parallel machine, shared memory systems, distributed memory systems, memory architecture
40	Lixin Zhang 0002, Venkata K. Pingali, Bharat Chandramouli, John B. Carter	Memory System Support for Dynamic Cache Line Assembly.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
40	Caroline Benveniste, Peter A. Franaszek, John T. Robinson	Cache-Memory Interfaces in Compressed Memory Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	memory compression, performance analysis, trace-driven simulation, cache design, Memory system design
40	Andreas Jürgen Lachenmann, Pedro José Marrón, Matthias Gauger, Daniel Minder, Olga Saukh, Kurt Rothermel	Removing the memory limitations of sensor networks with flash-based virtual memory.	EuroSys	2007	DBLP DOI BibTeX RDF	wireless sensor networks, flash memory, virtual memory, memory layout
39	Darren J. Kerbyson, Michael Lang 0003, Gene Patino, Hossein Amidi	An empirical performance analysis of commodity memories in commodity servers.	Memory System Performance	2004	DBLP DOI BibTeX RDF	performance analysis, performance measurement, memory modules, memory system performance
39	Michael C. Huang 0001, Jose Renau, Seung-Moon Yoo, Josep Torrellas	Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
39	Yoonseo Choi, Hwansoo Han	Shared heap management for memory-limited java virtual machines.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	heap sharing, memory protection unit, garbage collection, Dynamic memory management
39	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
39	Jung-Hoon Lee	Next High Performance and Low Power Flash Memory Package Structure.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	NAND-type, NOR-type, memory localities, buffer or cache memory, flash memory
39	Huu Hai Nguyen, Martin C. Rinard	Detecting and eliminating memory leaks using cyclic memory allocation.	ISMM	2007	DBLP DOI BibTeX RDF	cyclic memory allocation, failure-oblivious computing, memory leaks
38	Shoaib Kamil 0001, Parry Husbands, Leonid Oliker, John Shalf, Katherine A. Yelick	Impact of modern memory subsystems on cache optimizations for stencil computations.	Memory System Performance	2005	DBLP DOI BibTeX RDF	performance modeling, prefetch, stencil, cache blocking
38	Richard C. Murphy, Peter M. Kogge, Arun Rodrigues	The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
38	Quan T. Tran, Elizabeth D. Mynatt, Gina Calcaterra	Using Memory Aid to Build Memory Independence.	HCI (1)	2007	DBLP DOI BibTeX RDF	memory aid, personal autonomy, Home, self-efficacy, cooking
38	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
38	Nicholas Freitag McPhee, Riccardo Poli	Memory with memory: soft assignment in genetic programming.	GECCO	2008	DBLP DOI BibTeX RDF	linear GP, memory with memory, soft assignment, genetic programming, symbolic regression
38	Junkil Ryu, Chanik Park	Fast Initialization and Memory Management Techniques for Log-Based Flash Memory File Systems.	ICESS	2007	DBLP DOI BibTeX RDF	log-based file system, file system initialization, efficient memory management, flash memory, high performance
38	Bernhard Egger 0002, Jaejin Lee, Heonshik Shin	Scratchpad memory management for portable systems with a memory management unit.	EMSOFT	2006	DBLP DOI BibTeX RDF	compilers, virtual memory, paging, scratchpad, code placement, postpass optimization, portable systems, heterogeneous memory
38	Xiaogang Qiu, Michel Dubois 0001	Moving Address Translation Closer to Memory in Distributed Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	dynamic address translation, virtual-address caches, simulations, Multiprocessors, distributed shared memory, virtual memory
38	Mark S. Ackerman, Christine Halverson	Organizational Memory as Objects, Processes, and Trajectories: An Examination of Organizational Memory in Use.	Comput. Support. Cooperative Work.	2004	DBLP DOI BibTeX RDF	memory reuse, trajectories of information, knowledge management, distributed cognition, organizational memory, contextualization, boundary objects, corporate memory, information reuse, collective memory
37	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
37	David Elsweiler	Supporting human memory in personal information management.	SIGIR Forum	2008	DBLP DOI BibTeX RDF
37	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
37	Bernhard Egger 0002, Jaejin Lee, Heonshik Shin	Dynamic scratchpad memory management for code in portable systems with an MMU.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	compilers, virtual memory, paging, scratchpad, victim cache, Code placement, postpass optimization, portable systems, heterogeneous memory
37	Prabhat Mishra 0001, Mahesh Mamidipaka, Nikil D. Dutt	Processor-memory coexploration using an architecture description language.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Processor-memory codesign, memory exploration, design space exploration, architecture description language
37	Robert C. Steinke, Gary J. Nutt	A unified theory of shared memory consistency.	J. ACM	2004	DBLP DOI BibTeX RDF	memory consistency model lattice, memory consistency models, Distributed shared memory systems
37	Andreas Moshovos, Gurindar S. Sohi	Streamlining Inter-Operation Memory Communication via Data Dependence Prediction.	MICRO	1997	DBLP DOI BibTeX RDF	DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation
37	Anna M. del Corral, José M. Llabería	Access order to avoid inter-vector-conflicts in complex memory systems.	IPPS	1995	DBLP DOI BibTeX RDF	access order, inter-vector-conflicts, complex memory systems, vector processor accessing vectors, concurrent memory access, inter-conflicts, performance evaluation, performance, vector processor systems, memory subsystem, memory modules
37	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
37	Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic	A survey of distributed shared memory systems.	HICSS (1)	1995	DBLP DOI BibTeX RDF	shared memory programming paradigm, physically distributed memories, classification taxonomy, classification criteria, DSM mechanism, hybrid DSM implementations, distributed systems, parallel programming, shared memory multiprocessors, shared memory systems, distributed memory systems, distributed shared memory systems, DSM systems
37	Dan Grossman, Jeremy Manson, William W. Pugh	What do high-level memory models mean for transactions?	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
36	Vera A. Kazakova, Jena D. Hwang, Bonnie J. Dorr, Yorick Wilks, J. Blake Gage, Alex Memory, Mark A. Clark	SPLAIN: Augmenting Cybersecurity Warnings with Reasons and Data.	CoRR	2023	DBLP DOI BibTeX RDF
36	Donald Flywell Malanga, Memory Banda	ICT Use and Livelihoods of Women Microenterprises in Malawi.	CoRR	2021	DBLP BibTeX RDF
36	Faridah, Sunarno, Sentagi Sesotya Utami, Emilya Nurjani, Muhammad Ilham Hanif, Memory Motivanisman Waruwu, Rony Wijaya	Optimisation of the data point configurations in a building environmental monitoring system.	Int. J. Commun. Networks Distributed Syst.	2021	DBLP DOI BibTeX RDF
36	Mack Blackburn, Ning Yu, Alex Memory, W. Graham Mueller	Detecting and Annotating Narratives in Social Media: A Vision Paper.	ICWSM Workshops	2020	DBLP DOI BibTeX RDF
36	Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor	A Collective, Probabilistic Approach to Schema Mapping Using Diverse Noisy Evidence.	IEEE Trans. Knowl. Data Eng.	2019	DBLP DOI BibTeX RDF
36	Memory Rukasha, Felix Olu Bankole	Impact of e-Commerce on Corporate Governance and Ethics.	CONF-IRM	2019	DBLP BibTeX RDF
36	W. Graham Mueller, Alex Memory, Kyle Bartrem	Causal Discovery of Cyber Attack Phases.	ICMLA	2019	DBLP DOI BibTeX RDF
36	Memory Tauringana	An investigation into the adoption of e-commerce among older people.		2019	RDF
36	Alex Memory	Collective Relational Data Integration with Diverse and Noisy Evidence.		2019	RDF
36	Laura Smith, Rebecca O'Rourke, Memory Van Beek, Suzanne Bickerdike, Rania Alkhadragy	Local and Global Dimensions of a Clinical Skills E-book Development Project.	EC-TEL (Practitioner Proceedings)	2018	DBLP BibTeX RDF
36	Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor	A Collective, Probabilistic Approach to Schema Mapping: Appendix.	CoRR	2017	DBLP BibTeX RDF
36	Angelika Kimmig, Alex Memory, Renée J. Miller, Lise Getoor	A Collective, Probabilistic Approach to Schema Mapping.	ICDE	2017	DBLP DOI BibTeX RDF
36	Memory Machiridza	Misalignment challenges when integrating security requirements into mobile banking application development.	CONF-IRM	2016	DBLP BibTeX RDF
36	Henry G. Goldberg, William T. Young, Alex Memory, Ted E. Senator	Explaining and Aggregating Anomalies to Detect Insider Threats.	HICSS	2016	DBLP DOI BibTeX RDF
36	William T. Young, Alex Memory, Henry G. Goldberg, Ted E. Senator	Detecting Unknown Insider Threat Scenarios.	IEEE Symposium on Security and Privacy Workshops	2014	DBLP DOI BibTeX RDF
36	Ted E. Senator, Henry G. Goldberg, Alex Memory, William T. Young, Brad Rees, Robert Pierce, Daniel Huang 0003, Matthew Reardon, David A. Bader, Edmond Chow, Irfan A. Essa, Joshua Jones, Vinay Bettadapura, Duen Horng Chau, Oded Green, Oguz Kaya, Anita Zakrzewska, Erica Briscoe, Rudolph L. Mappus IV, Robert McColl, Lora Weiss, Thomas G. Dietterich, Alan Fern, Weng-Keen Wong, Shubhomoy Das, Andrew Emmott, Jed Irvine, Jay Yoon Lee, Danai Koutra, Christos Faloutsos, Daniel D. Corkill, Lisa Friedland, Amanda Gentzel, David D. Jensen	Detecting insider threats in a real corporate database of computer usage activity.	KDD	2013	DBLP DOI BibTeX RDF
36	William T. Young, Henry G. Goldberg, Alex Memory, James F. Sartain, Ted E. Senator	Use of Domain Knowledge to Detect Insider Threats in Computer Activities.	IEEE Symposium on Security and Privacy Workshops	2013	DBLP DOI BibTeX RDF
36	Alex Memory, Angelika Kimmig, Stephen H. Bach, Louiqa Raschid, Lise Getoor	Graph Summarization in Annotated Data Using Probabilistic Soft Logic.	URSW	2012	DBLP BibTeX RDF
36	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
36	V. Kim, T. Chen	Assessing SRAM test coverage for sub-micron CMOS technologies.	VTS	1997	DBLP DOI BibTeX RDF	submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
36	Gyungho Lee	An assessment of COMA multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	Cache Only Memory Architecture, Perfect Club Benchmark Suite, coherence policy, performance evaluation, performance, discrete event simulation, memory hierarchy, shared memory systems, distributed memory systems, update, trace driven simulations, cache storage, network traffic, miss ratio, distributed shared memory multiprocessors, shared address space, invalidate
36	Hung-Wei Tseng 0001, Han-Lin Li, Chia-Lin Yang	An energy-efficient virtual memory system with flash memory as the secondary storage.	ISLPED	2006	DBLP DOI BibTeX RDF	embedded storages, embedded systems, virtual memory, NAND flash memory, page replacement
36	Wolfgang K. Giloi, C. Hastedt, Friedrich Schön, Wolfgang Schröder-Preikschat	A Distributed Implementation of Shared Virtual Memory with Strong and Weak Coherence.	EDMCC	1991	DBLP DOI BibTeX RDF	virtual shared memory architecture, strong and weak data coherence, communication hardware, parallelizing compilers, Distributed memory architecture