Search results for "Microarchitecture"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
114	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
91	Kenneth Hoste, Lieven Eeckhout	Comparing Benchmarks Using Key Microarchitecture-Independent Characteristics.	IISWC	2006	DBLP DOI BibTeX RDF
82	Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001	Microarchitecture Configurations and Floorplanning Co-Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
73	Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve	Accurate microarchitecture-level fault modeling for studying hardware faults.	HPCA	2009	DBLP DOI BibTeX RDF
72	Victor V. Zyuban, Peter M. Kogge	Inherently Lower-Power High-Performance Superscalar Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Low power microarchitecture, multicluster architecture, energy-efficient configurations, energy models
71	Chang-Burm Cho, Wangyuan Zhang, Tao Li 0006	Informed Microarchitecture Design Space Exploration Using Workload Dynamics.	MICRO	2007	DBLP DOI BibTeX RDF
70	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
63	Wen-mei W. Hwu, Yale N. Patt	Exploiting horizontal and vertical concurrency via the HPSm microprocessor.	MICRO	1987	DBLP DOI BibTeX RDF
60	Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe	Statistical sampling of microarchitecture simulation.	ACM Trans. Model. Comput. Simul.	2006	DBLP DOI BibTeX RDF	Microarchitecture simulation, SPEC CPU2000 simulation, cold-start bias, simulation sampling, statistical sampling
60	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
60	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
59	Balakrishnan Iyer, Ramesh Karri, Israel Koren	Phantom redundancy: a high-level synthesis approach for manufacturability.	ICCAD	1995	DBLP DOI BibTeX RDF	fabrication-time reconfigurability, functional unit failure, microarchitecture synthesis, phantom redundancy, genetic algorithm, high level synthesis, high-level synthesis, redundancy, logic design, reconfigurable architectures, manufacturability, microarchitecture, circuit CAD
54	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration.	ISPASS	2009	DBLP DOI BibTeX RDF
54	Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant, P. J. Joseph	Microarchitecture Sensitive Empirical Models for Compiler Optimizations.	CGO	2007	DBLP DOI BibTeX RDF
54	Xin Fu, James Poe, Tao Li, José A. B. Fortes	Characterizing Microarchitecture Soft Error Vulnerability Phase Behavior.	MASCOTS	2006	DBLP DOI BibTeX RDF
54	Diana Marculescu, Emil Talpes	Variability and energy awareness: a microarchitecture-level perspective.	DAC	2005	DBLP DOI BibTeX RDF	GALS design, power consumption, variability
54	Roland E. Wunderlich, James C. Hoe	In-system FPGA prototyping of an itanium microarchitecture.	FPGA	2004	DBLP DOI BibTeX RDF
54	Roland E. Wunderlich, James C. Hoe	In-System FPGA Prototyping of an Itanium Microarchitecture.	ICCD	2004	DBLP DOI BibTeX RDF
54	Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi	Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures.	MICRO	2004	DBLP DOI BibTeX RDF
54	David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht	Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
54	Ho-Seop Kim, James E. Smith 0001	An Instruction Set and Microarchitecture for Instruction Level Distributed Processing.	ISCA	2002	DBLP DOI BibTeX RDF
54	Eric Rotenberg	Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems.	MICRO	2001	DBLP DOI BibTeX RDF
54	Trung A. Diep, Christopher Nelson, John Paul Shen	Performance Evaluation of the PowerPC 620 Microarchitecture.	ISCA	1995	DBLP DOI BibTeX RDF	PowerPC
52	Xin Fu, Tao Li 0006, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
52	Wangyuan Zhang, Tao Li 0006	Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.	MICRO	2008	DBLP DOI BibTeX RDF
52	Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross	A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation.	MICRO	2005	DBLP DOI BibTeX RDF
52	Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott	Dynamic frequency and voltage control for a multiple clock domain microarchitecture.	MICRO	2002	DBLP DOI BibTeX RDF
52	Fred J. Pollack	New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies.	MICRO	1999	DBLP DOI BibTeX RDF
52	Yale N. Patt	Microarchitecture choices (implementation of the VAX).	MICRO	1989	DBLP DOI BibTeX RDF	VAX
52	James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt	On tuning the microarchitecture of an HPS implementation of the VAX.	MICRO	1987	DBLP DOI BibTeX RDF
51	Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	3D packing, microarchitecture, 3D integration, thermal
51	Pedro Ángel Castillo Valdivieso, G. Fernández, Juan Julián Merelo Guervós, José Luis Bernier, Antonio Miguel Mora, Juan Luis Jiménez Laredo, Pablo García-Sánchez	Evolving Machine Microprograms: Application to the CODE2 Microarchitecture.	DCAI	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
51	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
51	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
45	Christophe Dubach, Timothy M. Jones 0001, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle	Portable compiler optimisation across embedded programs and microarchitectures using machine learning.	MICRO	2009	DBLP DOI BibTeX RDF	architecture/compiler co-design, machine learning, design-space exploration
45	Vimal K. Reddy, Eric Rotenberg	Coverage of a microarchitecture-level fault check regimen in a superscalar processor.	DSN	2008	DBLP DOI BibTeX RDF
45	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
45	Yogesh S. Mahajan, Sharad Malik	Automating Hazard Checking in Transaction-Level Microarchitecture Models.	FMCAD	2007	DBLP DOI BibTeX RDF
45	Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe	Statistical sampling of microarchitecture simulation.	IPDPS	2006	DBLP DOI BibTeX RDF
45	Thomas Lamotte, Françoise Peyrin, Jean-Marc Dinten	A prior model for bone microarchitecture reconstruction with a very limited number of projections.	ICIP (3)	2005	DBLP DOI BibTeX RDF
45	Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian	High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs.	DAC	2005	DBLP DOI BibTeX RDF	manotechnologies, reliability-delay trade-offs, performance optimization, fault tolerant microarchitectures
45	Kevin Skadron, Mircea R. Stan, Karthik Sankaranarayanan, Wei Huang 0004, Sivakumar Velusamy, David Tarjan	Temperature-aware microarchitecture: Modeling and implementation.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Dynamic compact thermal models, fetch gating, dynamic voltage scaling, feedback control, dynamic thermal management
45	Xinping Zhu, Wei Qin, Sharad Malik	Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	on-chip communication architecture, simulator synthesis, multiprocessor system, packet-switching network, design exploration, bus, retargetable simulation
45	Yuan Chou, Brian Fahs, Santosh G. Abraham	Microarchitecture Optimizations for Exploiting Memory-Level Parallelism.	ISCA	2004	DBLP DOI BibTeX RDF
45	Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe	SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling.	ISCA	2003	DBLP DOI BibTeX RDF
45	Nels Vander Zanden, Daniel Gajski	MILO: A Microarchitecture and Logic Optimizer.	DAC	1988	DBLP BibTeX RDF
44	Zhonglei Wang, Antonio Sánchez, Andreas Herkersdorf	SciSim: a software performance estimation framework using source code instrumentation.	WOSP	2008	DBLP DOI BibTeX RDF	debugging information, software performance estimation, source code instrumentation, microarchitecture
44	James Burns, Jean-Luc Gaudiot	SMT Layout Overhead and Scalability.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	layout area estimation, microarchitecture trade-off, processor architecture, SMT
44	Yiannakis Sazeides	Modeling Value Speculation.	HPCA	2002	DBLP DOI BibTeX RDF	microarchitecture modeling, speculation, value prediction, value speculation
44	Victor V. Zyuban	Unified architecture level energy-efficiency metric.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	performance, architecture, energy-efficiency, metric, power, energy, microarchitecture
43	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb	Die Stacking (3D) Microarchitecture.	MICRO	2006	DBLP DOI BibTeX RDF
43	Chen-Yong Cher, T. N. Vijaykumar	Skipper: a microarchitecture for exploiting control-flow independence.	MICRO	2001	DBLP DOI BibTeX RDF
43	Rahul Razdan, Michael D. Smith 0001	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
43	Edil S. T. Fernandes	Microarchitecture modelling through ADL.	MICRO	1988	DBLP BibTeX RDF
42	Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik	Supporting RTL flow compatibility in a microarchitecture-level design framework.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	microarchitecture level, transactions, formal models, hierarchical design, hardware resources
42	Ronny Ronen, Antonio González 0001	Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences.	IEEE Micro	2007	DBLP DOI BibTeX RDF	programmable architecture, performance evaluation, fault tolerance, microarchitecture, multicore systems, wireless protocols
42	Niti Madan, Rajeev Balasubramonian	Leveraging 3D Technology for Improved Reliability.	MICRO	2007	DBLP DOI BibTeX RDF	redundant multi-threading, 3D die-stacking, dynamic timing errors, power-efficient microarchitecture, on-chip temperature, reliability, soft errors, parameter variation
42	Grigorios Magklis, Pedro Chaparro, José González 0002, Antonio González 0001	Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.	ISLPED	2006	DBLP DOI BibTeX RDF	MCD, energy efficiency, DVS, microarchitecture, GALS
42	Sarita V. Adve, Pia N. Sanda	Guest Editors' Introduction: Reliability-Aware Microarchitecture.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability-aware microarchitecture, reliability management, soft errors, CMOS scaling
42	Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe	TurboSMARTS: accurate microarchitecture simulation sampling in minutes.	SIGMETRICS	2005	DBLP DOI BibTeX RDF	checkpointed microarchitecture simulation, simulation sampling
42	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Microarchitecture-aware floorplanning using a statistical design of experiments approach.	DAC	2005	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, wire pipelining
42	Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis	Microarchitecture evaluation with physical planning.	DAC	2003	DBLP DOI BibTeX RDF	microarchitecture evaluation, physical planning
37	Xin Fu, Tao Li, José A. B. Fortes	Soft error vulnerability aware process variation mitigation.	HPCA	2009	DBLP DOI BibTeX RDF
37	Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque	Evaluation of the field-programmable cache: performance and energy consumption.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	adaptive processors, reconfigurable cache memory, static and dynamic energy consumption, performance evaluation, run-time adaptation
37	Alex Orailoglu, Ramesh Karri	Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
35	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
35	Kenneth Hoste, Lieven Eeckhout	Microarchitecture-Independent Workload Characterization.	IEEE Micro	2007	DBLP DOI BibTeX RDF	workload characterization, modeling techniques, measurement techniques, performance attributes
35	Stijn Eyerman, Lieven Eeckhout, James E. Smith 0001	Studying Compiler-Microarchitecture Interactions through Interval Analysis.	PACT	2007	DBLP DOI BibTeX RDF
35	Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin	Verification Driven Formal Architecture and Microarchitecture Modeling.	MEMOCODE	2007	DBLP DOI BibTeX RDF
35	Rong Ji, Xianjun Zeng, Liang Chen, Junfeng Zhang	The Implementation and Design of a Low-Power Clock Distribution Microarchitecture.	IEEE NAS	2007	DBLP DOI BibTeX RDF
35	Fei Guo, Yan Solihin, Li Zhao 0002, Ravishankar R. Iyer 0001	A Framework for Providing Quality of Service in Chip Multi-Processors.	MICRO	2007	DBLP DOI BibTeX RDF
35	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Power analysis
35	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu 0001, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
35	Diana Marculescu, Emil Talpes	Energy Awareness and Uncertainty in Microarchitecture-Level Design.	IEEE Micro	2005	DBLP DOI BibTeX RDF	gate length, on-chip temperature variations, variability metric, Energy awareness
35	Weiping Liao, Joseph M. Basile, Lei He 0001	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt	Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
35	Jaume Abella 0001, Antonio González 0001	Inherently Workload-Balanced Clustered Microarchitecture.	IPDPS	2005	DBLP DOI BibTeX RDF
35	Lei Wang 0003	Error-tolerance memory Microarchitecture via Dynamic Multithreading.	ICCD	2005	DBLP DOI BibTeX RDF
35	Ethan Schuchman, T. N. Vijaykumar	Rescue: A Microarchitecture for Testability and Defect Tolerance.	ISCA	2005	DBLP DOI BibTeX RDF
35	Minglong Shao, Anastassia Ailamaki, Babak Falsafi	DBmbench: fast and accurate database workload representation on modern microarchitecture.	CASCON	2005	DBLP BibTeX RDF
35	Juanjo Noguera, Rosa M. Badia	Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	Adaptable architectures and microarchitectures, runtime support for dynamic reconfiguration, dynamic scheduling
35	Yoav Almog, Roni Rosner, Naftali Schwartz, Ari Schmorak	Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture.	CGO	2004	DBLP DOI BibTeX RDF
35	Anne Bracy, Prashant Prahlad, Amir Roth	Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth.	MICRO	2004	DBLP DOI BibTeX RDF
35	Kevin Skadron, Mircea R. Stan, Wei Huang 0004, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan	Temperature-Aware Microarchitecture.	ISCA	2003	DBLP DOI BibTeX RDF
35	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan	Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.	MICRO	2003	DBLP DOI BibTeX RDF
35	Ranjit Jhala, Kenneth L. McMillan	Microarchitecture Verification by Compositional Model Checking.	CAV	2001	DBLP DOI BibTeX RDF
35	Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta	Performance characterization of a hardware mechanism for dynamic optimization.	MICRO	2001	DBLP DOI BibTeX RDF
35	David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
35	Eric Rotenberg, Steve Bennett, James E. Smith 0001	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
34	José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo	Modelling Asynchronous Systems using Probability Distribution Functions.	PDP	2008	DBLP DOI BibTeX RDF	modelling, asynchronous, microarchitecture
34	Pedro Ángel Castillo Valdivieso, G. Fernández, Antonio Mora García, Juan Julián Merelo Guervós, José Luis Bernier, Alberto Prieto	Evolving machine microprograms.	GECCO	2008	DBLP DOI BibTeX RDF	evolutionary computation techniques, optimization, computer architecture, microarchitecture, microprogramming, automatic design
34	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001	A Retargetable Software Timing Analyzer Using Architecture Description Language.	ASP-DAC	2007	DBLP DOI BibTeX RDF	retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis
34	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
34	Nitzan Weinberg, David Nagle	Dynamic Elimination of Pointer-Expressions.	IEEE PACT	1998	DBLP DOI BibTeX RDF	pointer-expression, sphinx, sub-expression, SPECint95, memory address, performance analysis, compiler, locality, speech recognition, dynamic, microprocessor, mpeg, cache memory, microarchitecture, jpeg, value, spatial, memory bandwidth, data reuse, temporal, pointer, conditional execution
33	Gerasimos Gerogiannis, Josep Torrellas	Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making.	MICRO	2023	DBLP DOI BibTeX RDF
33	Chen Bai, Jiayi Huang 0001, Xuechao Wei, Yuzhe Ma, Sicheng Li, Hongzhong Zheng, Bei Yu 0001, Yuan Xie 0001	ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis.	MICRO	2023	DBLP DOI BibTeX RDF
33	Joshua J. Yi	Microarchitecture Patents Over Time and Interesting Early Microarchitecture Patents.	IEEE Micro	2021	DBLP DOI BibTeX RDF
33	Jaeguk Ahn, Jiho Kim, Hans Kasan, Zhixian Jin, Leila Delshadtehrani, WonJun Song, Ajay Joshi, John Kim	Network-on-Chip Microarchitecture-based Covert Channel in GPUs.	MICRO	2021	DBLP DOI BibTeX RDF
33	Vasileios Tsoutsouras, Orestis Kaparounakis, Bilgesu Arif Bilgin, Chatura Samarakoon, James Timothy Meech, Jan Heck, Phillip Stanley-Marbell	The Laplace Microarchitecture for Tracking Data Uncertainty and Its Implementation in a RISC-V Processor.	MICRO	2021	DBLP DOI BibTeX RDF