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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 7 occurrences of 7 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Darshan Desai, Gerolf Hoflehner, Arun Kejariwal, Daniel M. Lavery, Alexandru Nicolau, Alexander V. Veidenbaum, Cameron McNairy |
Performance Characterization of ItaniumĀ® 2-Based Montecito Processor. |
SPEC Benchmark Workshop |
2009 |
DBLP DOI BibTeX RDF |
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67 | Cameron McNairy, Rohit Bhatia |
Montecito: A Dual-Core, Dual-Thread Itanium Processor. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance |
40 | Yifei Cui, Deqiang Cheng, Dave Chan |
Investigation of Post-Fire Debris Flows in Montecito. |
ISPRS Int. J. Geo Inf. |
2019 |
DBLP DOI BibTeX RDF |
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36 | Eric S. Fetzer |
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design. |
IEEE Des. Test Comput. |
2006 |
DBLP DOI BibTeX RDF |
dual core, Itanium microprocessor, Montecito, adaptive circuits, cache safe technology, active clock deskew, process variation, power measurement |
26 | Dong Hyuk Woo, Hsien-Hsin S. Lee |
PROPHET: goal-oriented provisioning for highly tunable multicore processors in cloud computing. |
ACM SIGOPS Oper. Syst. Rev. |
2009 |
DBLP DOI BibTeX RDF |
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26 | Sachin S. Sapatnekar |
Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
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