Search results for "Multiplier"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
92	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
88	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
75	Nuno Bandeira, Ken Vaccaro, James A. Howard	A Two's Complement Array Multiplier Using True Values of the Operands.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Pezaris multiplier, Baugh-Wooley multiplier, celluar-subtractor multiplier, Array multiplier, parallel multiplier, binary multiplication
75	Chang Han Kim, Yongtae Kim, Nam Su Chang, IlHwan Park	Modified Serial Multipliers for Type-IV Gaussian Normal Bases.	INDOCRYPT	2005	DBLP DOI BibTeX RDF	serial multiplier, Finite fields, ECC, Massey-Omura multiplier, Gaussian Normal Basis
71	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
66	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
66	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
66	Xu Zhou, Zhimin Tang	A New Architecture of a Fast Floating-Point Multiplier.	APPT	2003	DBLP DOI BibTeX RDF	Floating-point Multiplier, Processor
66	Arash Reyhani-Masoleh, M. Anwarul Hasan	A New Construction of Massey-Omura Parallel Multiplier over GF(2m).	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	optimal normal bases, Finite field, Massey-Omura multiplier, all-one polynomial
63	Peter Kornerup	A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
60	Hyeong-Ju Kang, In-Cheol Park	Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
59	Sandeep S. Kumar, Thomas J. Wollinger, Christof Paar	Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	least significant digit multiplier, elliptic/hyperelliptic curve cryptography, public key cryptography, digit serial multiplier, Bit serial multiplier
59	Johann Großschädl	A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m).	CHES	2001	DBLP DOI BibTeX RDF	iterative modulo multiplication, polynomial basis representation, bit-serial multiplier architecture, smart card crypto-coprocessor, Elliptic curve cryptography, finite field arithmetic
59	Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal	A Radix-8 CMOS S/390 Multiplier.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit
59	Belle W. Y. Wei, He Du, Honglu Chen	A complex-number multiplier using radix-4 digits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	complex-number multiplier, radix-4 digits, arithmetic datapath, complex-number digital signal processor, binary signed digits, fast multiplication, compact layout, three-multiplication scheme, radix-4 operands, delays, delay, encoding, digital arithmetic, multiplying circuits, binary additions, coding scheme
59	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
58	Alexandre F. Tenca, Georgi Todorov, Çetin Kaya Koç	High-Radix Design of a Scalable Modular Multiplier.	CHES	2001	DBLP DOI BibTeX RDF	modular multiplier, montgomery multiplier, high-radix, scalable architecture
58	Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar	A multiplier generator for Xilinx FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs
56	Marcelo E. Kaihara, Naofumi Takagi	Bipartite Modular Multiplication Method.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Algorithms, Computer arithmetic
56	Nicola Petra, Davide De Caro, Antonio G. M. Strollo	A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	VLSI, High-Performance, Digital, Reed-Solomon codes, Arithmetic, finite field multiplication, polynomial basis
56	Jongsun Park 0001, Khurram Muhammad, Kaushik Roy 0001	High-performance FIR filter design based on sharing multiplication.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
55	Arash Reyhani-Masoleh, M. Anwarul Hasan	On Low Complexity Bit Parallel Polynomial Basis Multipliers.	CHES	2003	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, pentanomial, trinomial and equally-spaced polynomial, polynomial basis
54	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	Mob. Networks Appl.	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
53	Charles Tsen, Sonia González-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton	A Combined Decimal and Binary Floating-Point Multiplier.	ASAP	2009	DBLP DOI BibTeX RDF
53	Martin Novotný, Jan Schmidt	General Digit-Serial Normal Basis Multiplier with Distributed Overlap.	DSD	2007	DBLP DOI BibTeX RDF
53	Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar	A novel multiplexer based truncated array multiplier.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
53	Lei Zhou, Yong Ping Xu, Fujiang Lin	A gigahertz wideband CMOS multiplier for UWB transceiver.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
53	Kip C. Killpack, Eric Mercer, Chris J. Myers	A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
53	Jinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang	Low-power fixed-width array multipliers.	ISLPED	2004	DBLP DOI BibTeX RDF	fixed-width multiplier, left-to-right multiplier, reduced-width multiplier, low power
53	Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang	Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers.	ICCD	1996	DBLP DOI BibTeX RDF	pipelined multipliers, nonpipelined multipliers, Baugh-Wooley multiplier, binary tree multiplier, Wallace tree multiplier, STDs, sub circuits, energy values, cubic dependence, word length, quadratic dependence, digital CMOS circuits, CMOS adder, low power arithmetic units, power consumption, power consumption, switching activity, state transition diagrams
52	Chua-Chin Wang, Gang-Neng Sung	Low-Power Multiplier Design Using a Bypassing Technique.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Low power multiplier, Timing control, Partial product, Bypassing
52	Sun-Mi Park, Ku-Young Chang, Dowon Hong	Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	shifted polynomial basis, irreducible pentanomial, finite field arithmetic, Bit-parallel multiplier
52	Ku-Young Chang, Dowon Hong, Hyun Sook Cho	Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Karatsuba method, AOP, finite field arithmetic, redundant representation, Bit-parallel multiplier
52	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m).	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, finite fields, multiplier, single stuck-at fault
52	Yeshwant Kolla, Yong-Bin Kim, John Carter	A novel 32-bit scalable multiplier architecture.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	CMOS VLSI, architecture, multiplier
52	Hak-soo Yu, Jacob A. Abraham	An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	3-bit-scan, power-delay-area tradeoffs, synchronous sequential, multiplier, partial product
52	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
51	Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou	A high-speed radix-4 multiplexer-based array multiplier.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	modified booth, multiplexer-based, radix-4 multiplier, array multiplier
50	Ron S. Waters, Earl E. Swartzlander Jr.	A Reduced Complexity Wallace Multiplier Reduction.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	High-speed multiplier, Wallace multiplier, Dadda multiplier
49	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Binary Multiplication Radix-32 and Radix-256.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
48	Soonhak Kwon, Kris Gaj, Chang Hoon Kim, Chun Pyo Hong	Efficient Linear Array for Multiplication in GF(2m) Using a Normal Basis for Elliptic Curve Cryptography.	CHES	2004	DBLP DOI BibTeX RDF	finite field, elliptic curve cryptography, Massey-Omura multiplier, Gaussian normal basis, critical path delay
46	Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle	A parallel IEEE P754 decimal floating-point multiplier.	ICCD	2007	DBLP DOI BibTeX RDF
46	Chih-Hsing Lin, Ching-Te Chiu	A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
46	Saurabh Singh, K. Radhakrishna Rao	Low Voltage Analogue Multiplier.	APCCAS	2006	DBLP DOI BibTeX RDF
46	Sai Mohan Kilambi, Behrouz Nowrouzian	A Genetic Algorithm Employing Correlative Roulette Selection for Optimization of FRM Digital Filters over CSD Multiplier Coefficient Space.	APCCAS	2006	DBLP DOI BibTeX RDF
46	Bo Yang 0010, Nikhil Joshi, Ramesh Karri	A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
46	Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng	Integrated algorithmic logical and physical design of integer multiplier.	ASP-DAC	2005	DBLP DOI BibTeX RDF	booth, interconnect, partial product, TDM
46	Amir Khatibzadeh, Kaamran Raahemifar	A Novel Design of a 6-GHz 8 X 8-b Pipelined Multiplier.	IWSOC	2005	DBLP DOI BibTeX RDF
46	Magnus Själander, Henrik Eriksson, Per Larsson-Edefors	An Efficient Twin-Precision Multiplier.	ICCD	2004	DBLP DOI BibTeX RDF
46	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
46	Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale	Design guidelines for reconfigurable multiplier blocks.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
46	Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb Lee	A fast-serial finite field multiplier without increasing the number of registers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
46	Ahmad A. Hiasat	New Efficient Structure for a Modular Multiplier for RNS.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	hardware requirements, VLSI, computer arithmetic, Residue number system, time delay, modular multiplication
46	Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy 0001	Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.	ICCD	1999	DBLP DOI BibTeX RDF
46	Vesselin K. Vassilev, Julian F. Miller, Terence C. Fogarty	On the Nature of Two-Bit Multiplier Landscapes.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
46	Dinesh Somasekhar, V. Visvanathan	A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
46	Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli	Multi-gigabit GCM-AES Architecture Optimized for FPGAs.	CHES	2007	DBLP DOI BibTeX RDF	Galois/Counter Mode (GCM), hybrid multiplier, Field Programmable Gate Array (FPGA), Very Large Scale Integration (VLSI), Advanced Encryption Standard (AES), high throughput, digit-serial multiplier, bit-parallel multiplier
45	Tae Ho Kim, Sang Chul Kim, Chang Hoon Kim, Chun Pyo Hong	Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m).	DELTA	2008	DBLP DOI BibTeX RDF	Multi-Precision CSA, Scalable Multiplier, VLSI, Montgomery Multiplication
45	Chiou-Yng Lee, Che Wun Chiou, Jim-Min Lin	Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m).	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	cryptography, fault-tolerant computing, fault detection, multiplier, finite fields arithmetic
45	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
45	Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
45	Berk Sunar, Çetin Kaya Koç	An Efficient Optimal Normal Basis Type II Multiplier.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Galois field, space complexity, optimal normal basis, Massey-Omura multiplier
45	Rong Lin	A Reconfigurable Low-Power High-Performance Matrix Multiplier Design.	ISQED	2000	DBLP DOI BibTeX RDF	low-power CMOS circuits, parallel counter-multiplier circuits, reconfigurable architecture, Matrix multiplication
45	Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar	VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder.	VLSI Design	1996	DBLP DOI BibTeX RDF	Digital Multiplier and Adder, VLSI Implementation of Neural Networks, Artificial Neural Networks (ANN)
45	Charles U. Martel, Vojin G. Oklobdzija, R. Ravi 0001, Paul F. Stelling	Design Strategies for Optimal Multiplier Circuits.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	Algorithms, Circuit design, Partial product reduction, Multiplier design
44	Zhijun Huang, Milos D. Ercegovac	High-Performance Low-Power Left-to-Right Array Multiplier Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Left-to-right array multiplier, tree multiplier, layout regularity, low-power design, high-performance design
44	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
43	Abner Corrêa Barros, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Paulo Sérgio Brandão do Nascimento, Ângelo Mazer, João Paulo Fernandes Barbosa, Bruno P. Neves, Ismael Santos 0001, Manoel Eusébio de Lima	Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.	SBCCI	2008	DBLP DOI BibTeX RDF	FPGA, scientific computing, floating-point, HPC
43	Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis	A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
42	Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu	Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division
42	Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou	Sub-word and reduced-width Booth multipliers for DSP applications.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
42	Kazimierz Wiatr, Ernest Jamro	Implementation of Multipliers in FPGA Structures.	ISQED	2001	DBLP DOI BibTeX RDF
42	George Havas, Jean-Pierre Seifert	The Complexity of the Extended GCD Problem.	MFCS	1999	DBLP DOI BibTeX RDF	computational problems of diophantine equations, extended gcd computations, Approximation algorithms, NP-hardness, probabilistically checkable proofs, interactive proof systems
41	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
41	Abdulah Abdulah Zadeh	A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation.	ARES	2008	DBLP DOI BibTeX RDF	Hybrid multiplier, GF, Polynomial (Standard) Basis, Finite Field
41	Johann Großschädl	High-Speed RSA Hardware Based on Barret's Modular Reduction Method.	CHES	2000	DBLP DOI BibTeX RDF	RSA algorithm, partial parallel multiplier, full-custom VLSI design, pipelining, Public-key cryptography, modular arithmetic
41	David M. Mandelbaum, Stefanie G. Mandelbaum	A Fast, Efficient Parallel-Acting Method of Generating Functions Defined by Power Series, Including Logarithm, Exponential, and Sine, Cosine.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	multinomials, multiplier tree, partitions, functions, Arrays, exponential, logarithm, sine, power series, cosine
40	Arash Reyhani-Masoleh	A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases.	CHES	2008	DBLP DOI BibTeX RDF	Finite or Galois field, Mastrovito multiplier, polynomial basis, bit-serial multiplier
40	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
39	Md. Ibrahim Faisal, Magdy A. Bayoumi	A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers.	ISCAS	2008	DBLP DOI BibTeX RDF
39	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
39	Chang Sun, Hongjun Wang 0004, Hua Li, Tai-Hoon Kim	Perceptually Adaptive Lagrange Multiplier for Rate-Distortion Optimization in H.264.	FGCN (1)	2007	DBLP DOI BibTeX RDF
39	Yunhua Wang, Linda DeBrunner, Dayong Zhou, Victor E. DeBrunner	A Multiplier Structure Based on a Novel Real-time CSD Recoding.	ISCAS	2007	DBLP DOI BibTeX RDF
39	Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas	An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).	DSD	2006	DBLP DOI BibTeX RDF
39	Zih-Heng Chen, Ming-Haw Jing, Trieu-Kien Truong, Yaotsu Chang	Another Look at the Sequential Multiplier over Normal Bases.	APCCAS	2006	DBLP DOI BibTeX RDF
39	Suryanarayana Tatapudi, José G. Delgado-Frias	A High Performance Hybrid Wave-Pipelined Multiplier.	ISVLSI	2005	DBLP DOI BibTeX RDF
39	Justin Hensley, Anselmo Lastra, Montek Singh	A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier.	ASYNC	2005	DBLP DOI BibTeX RDF
39	Jieh-Hwang Yen, Lan-Rong Dung, Chi-Yuan Shen	Design of power-aware multiplier with graceful quality-power trade-offs.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
39	Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang	A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
39	Soonhak Kwon	A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
39	Minyue Fu 0001, Soura Dasgupta, Yeng Chai Soh	Integral quadratic constraint approach vs. multiplier approach.	ICARCV	2002	DBLP DOI BibTeX RDF
39	Kiwon Choi, Minkyu Song	Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
39	Lijun Gao, Keshab K. Parhi	Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Mohammad K. Ibrahim, Abulaziz Almulhem	Bit-level pipelined digit serial GF(2m) multiplier.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
39	Hyun-Sung Kim 0001, Kee-Young Yoo	Area Efficient Exponentiation Using Modular Multiplier/Squarer in GF(2m.	COCOON	2001	DBLP DOI BibTeX RDF
39	Shyh-Jye Jou, Hui-Hsuan Wang	Fixed-Width Multiplier for DSP Application.	ICCD	2000	DBLP DOI BibTeX RDF
39	Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Fast Multiplier Cores.	DATE	1999	DBLP DOI BibTeX RDF
39	Chi-Hung Lin, Mohammed Ismail 0001	A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
39	Deepak Kapur, Mahadevan Subramaniam	Mechanically Verifying a Family of Multiplier Circuits.	CAV	1996	DBLP DOI BibTeX RDF