Search results for "PLD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
136	Dewayne E. Perry, Jeff Kramer	Architectural Description.	ESPRIT ARES Workshop	1998	DBLP DOI BibTeX RDF
94	Jae-Jin Lee, Gi-Yong Song	Super Semi-systolic Array-Based Application-Specific PLD Architecture.	ARC	2006	DBLP DOI BibTeX RDF
77	Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song	Design of a Reversible PLD Architecture.	ARC	2007	DBLP DOI BibTeX RDF
77	Jae-Jin Lee, Gi-Yong Song	Design of an application-specific PLD architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
77	Ding-Yi Chen, Xue Li 0001	PLD: A Distillation Algorithm for Misclassified Documents.	WAIM	2004	DBLP DOI BibTeX RDF
68	Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi	Using eye tracking to investigate important cues for representative creature motion.	ETRA	2010	DBLP DOI BibTeX RDF	point-light display, animation, perception, eyetracking
68	Harald Øverby	How the packet length distribution influences the packet loss rate in an optical packet switch.	AICT/ICIW	2006	DBLP DOI BibTeX RDF
68	Adrian J. Hilton, Jon G. Hall	High-Integrity Interfacing to Programmable Logic with Ada.	Ada-Europe	2004	DBLP DOI BibTeX RDF
51	Christoph Hoyer, Gerhard Chroust	Evolving Standard Process Reference Models for Product Line Development.	EUROMICRO-SEAA	2006	DBLP DOI BibTeX RDF
51	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	New Parameter for Balancing Two Independent Measures in Routing Path.	ICCSA (4)	2004	DBLP DOI BibTeX RDF
51	Valeri Solovjev	Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines.	DSD	2001	DBLP DOI BibTeX RDF
51	Michael D. Hutton	Interconnect prediction for programmable logic devices.	SLIP	2001	DBLP DOI BibTeX RDF	interconnect prodiction, wireability, architecture, programmable logic device
51	Alireza Kaviani, Stephen Dean Brown	Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.	FPGA	2000	DBLP DOI BibTeX RDF
43	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
43	Adam Dabrowski, Pawel Pawlowski	Benchmark problems of Signal Processing and Control for Testing Emergent Architectures and Programming Techniques of DSP's, FASIC's, and PLD's.	CISIM	2007	DBLP DOI BibTeX RDF
43	M. Hutton, K. Adibsamii, A. Leaver	Adaptive delay estimation for partitioning-driven PLD placement.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
43	Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev	Interconnect enhancements for a high-speed PLD architecture.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, architecture, interconnect, programmable logic
43	Hiroshi Tsutsui, K. Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura	A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
43	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
42	FengYing Wang, RuZhi Wang, Wei Zhao, XueMei Song, Bo Wang, Hui Yan	Field emission properties of amorphous GaN ultrathin films fabricated by pulsed laser deposition.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	field emission, amorphous gallium nitride (a-GaN), pulsed laser deposition (PLD), work function
34	Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi	Lions and tigers and bears: investigating cues for expressive creature motion.	SIGGRAPH Posters	2010	DBLP DOI BibTeX RDF
34	Tomoji Kishi, Natsuko Noda, Takuya Katayama	Design Verification for Product Line Development.	SPLC	2005	DBLP DOI BibTeX RDF
34	Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio	TOP: An Algorithm for Three-Level Optimization of PLDs.	DATE	2000	DBLP DOI BibTeX RDF
26	Brian Butka, Janusz Zalewski, Andrew J. Kornecki	Issues in Tool Qualification for Safety-Critical Hardware: What Formal Approaches Can and Cannot Do.	SAFECOMP	2009	DBLP DOI BibTeX RDF	Tool Qualification, Formal Methods, Safety-Critical Systems, Hardware Design, HDL, PLD
26	Jason Cong, Hui Huang 0001, Xin Yuan 0005	Technology mapping and architecture evalution for k/m-macrocell-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	FPGA, technology mapping, CPLD, PLD
26	Ian Kuon, Aaron Egier, Jonathan Rose	Design, layout and verification of an FPGA using automated tools.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
26	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
26	Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	An Approach for Detecting Multiple Faulty FPGA Logic Blocks.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	fault tolerance, FPGA, multiple faults, C-testability, PLD
26	Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi	On the Complexity of Sequential Testing in Configurable FPGAs.	DFT	1998	DBLP DOI BibTeX RDF	FPGA, pipeline, PLD, sequential testing, iterative array
26	Avinash Munshi, Fred J. Meyer, Fabrizio Lombardi	A New Method for Testing EEPLA's.	DFT	1998	DBLP DOI BibTeX RDF	EEPLA, testing, multiple faults, PLD
26	S. Thumilvannan, R. Balamanigandan	Correlated feature-based diabetes and heart disease risk-level classification in IoT environment using PLD-SSL-RBM.	J. Intell. Fuzzy Syst.	2023	DBLP DOI BibTeX RDF
26	Alireza Moazzeni, Md Tawsif Rahman Chowdhury, Christopher Rouleau, Gozde Tutuncuoglu	Engineering the Device Performance of PLD Grown Tantalum Oxide based RRAM Devices.	eIT	2023	DBLP DOI BibTeX RDF
26	Yucheng Tang, Yipeng Hu, Jing Li, Hu Lin, Xiang Xu, Ke Huang, Hongxiang Lin	PLD-AL: Pseudo-label Divergence-Based Active Learning in Carotid Intima-Media Segmentation for Ultrasound Images.	MICCAI (2)	2023	DBLP DOI BibTeX RDF
26	Baosheng Zhang	PLD-SLAM: A Real-Time Visual SLAM Using Points and Line Segments in Dynamic Scenes.	CoRR	2022	DBLP DOI BibTeX RDF
26	S. Moreno-Alcocer, Karen Rodriguez-Rosales, Jorge Cruz-Gómez, Jose Santos-Cruz, A. Guillén-Cervantes, Francisco Javier De Moure-Flores	Substrate temperature effect of CdTe films grown by PLD on photovoltaic properties of CdS/CdTe solar cells.	CCE	2022	DBLP DOI BibTeX RDF
26	Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, André DeHon	PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development.	ASPLOS	2022	DBLP DOI BibTeX RDF
26	Chenyang Zhang, Teng Huang, Rongchun Zhang, Xuefeng Yi	PLD-SLAM: A New RGB-D SLAM Method with Point and Line Features for Indoor Dynamic Scene.	ISPRS Int. J. Geo Inf.	2021	DBLP DOI BibTeX RDF
26	Dedi Priadi, Margaretha Suliyanti, Rusman Kosasih	PLD Nd: YAG Process for Coating Pin Insert SKD 61 which used for Aluminum Die Casting.	APCoRISE	2020	DBLP BibTeX RDF
26	Sowmiya C., Arun Kumar Thittai	Enhancing Depth of Penetration in PLD-Based Photoacoustic Imaging: Preliminary Results.	EMBC	2019	DBLP DOI BibTeX RDF
26	Sowmiya C., Arun Kumar Thittai	Noise Reduction in Inherently low-SNR PLD-based PAT images.	TENCON	2019	DBLP DOI BibTeX RDF
26	Antonio V. Silva Neto, Lucio Flavio Vismari, Ricardo Alexandre Veiga Gimenes, Daniel Baraldi Sesso, Jorge Rady de Almeida Jr., Paulo Sérgio Cugnasca, João Batista Camargo Jr.	A Practical Analytical Approach to Increase Confidence in PLD-Based Systems Safety Analysis.	IEEE Syst. J.	2018	DBLP DOI BibTeX RDF
26	Przemyslaw Plóciennik, Anna Zawadzka, Janusz Strzelecki, Zbigniew Lukasiak, Andrzej Korcala	Pulsed laser deposition (PLD) of hafnium oxide thin films.	ICTON	2014	DBLP DOI BibTeX RDF
26	A. V. Borlyakov, V. M. Gevorkayn, I. A. Yashin	Pulse interferences detection and measurement PLD-based algorithm: Algorithm and functional diagram.	MECO	2014	DBLP DOI BibTeX RDF
26	G. P. Aksenova	A matrix method for PLD failure localization.	Autom. Remote. Control.	2013	DBLP DOI BibTeX RDF
26	Muneer Shaik, Ibrahim M. Abdel-Motaleb	Effect of growth temperature on the material properties of PLD-grown Bi2Te3 and Sb2Te3.	EIT	2013	DBLP DOI BibTeX RDF
26	Muneer Shaik, Ibrahim M. Abdel-Motaleb	Investigation of the electrical properties of PLD-grown Bi2Te3 and Sb2Te2.	EIT	2013	DBLP DOI BibTeX RDF
26	Muneer Shaik, Ibrahim M. Abdel-Motaleb	Investigation of the optical properties of PLD-grown Bi2Te3 and Sb2Te3.	EIT	2013	DBLP DOI BibTeX RDF
26	Carla Ferreira 0002, Sérgio Monteiro, João Monteiro	Automatic Generation of C-code or PLD Circuits under SFC Graphical Environment	CoRR	2012	DBLP BibTeX RDF
26	Syed Farhan Mohiudin, Martin Kocanda, Ibrahim M. Abdel-Motaleb	Optical properties of PLD-deposited barium strontium titanate (BaxSr1-xTiO3) thin films.	EIT	2012	DBLP DOI BibTeX RDF
26	Javier García-Zubía, Pablo Orduña, Ignacio Angulo, Unai Hernández, Olga Dziabenko, Diego López-de-Ipiña, Luis Rodriguez-Gil	Application and user perceptions of using the WebLab-Deusto-PLD in technical education.	FIE	2011	DBLP DOI BibTeX RDF
26	Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song	Design and verification of an application-specific PLD using VHDL and SystemVerilog.	ASICON	2011	DBLP DOI BibTeX RDF
26	S. L. Smitha, R. G. Abhilash Kumar, K. G. Gopchandran	Surface plasmon resonance engineering of gold nanoparticles using off-axis PLD technique.	ICUMT	2010	DBLP DOI BibTeX RDF
26	Gregg Collins, David Elam, Ross Hackworth, Rama Kotha, Arturo Ayon, Andrey Chabanov, Chonglin Chen	Pulsed laser deposition (PLD) employed in the fabrication of low temperature barium titanate (BTO) films on carbon fibers.	CONIELECOMP	2010	DBLP DOI BibTeX RDF
26	Simar Maangat, Toan Nguyen, Wilson Wong, Sergey Y. Shumarayev, Tina Tran, Tim Hoang, Richard Cliff	Receiver Offset Cancellation in 90-nm PLD Integrated SERDES.	CICC	2007	DBLP DOI BibTeX RDF
26	Jae-Jin Lee, Gi-Yong Song	A New Application-Specific PLD Architecture.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
26	Tomonori Izumi, Shin'ichi Kouyama, Hiroyuki Ochi, Yukihiro Nakamura	An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
26	Jacobo Álvarez, Jorge Marcos, Santiago Fernández	Safe PLD-based Programmable Controllers.	FPL	2005	DBLP DOI BibTeX RDF
26	Adrian J. Hilton, Jon G. Hall	Developing critical systems with PLD components.	FMICS	2005	DBLP DOI BibTeX RDF
26	M. Muthulakshmi, J. Robert Heath, Kenneth L. Calvert, James Griffioen	ESP: a flexible, high-performance, PLD-based network service.	ICC	2004	DBLP DOI BibTeX RDF
26	Dushyanthan Puvanendrampillai, John B. O. Mitchell	Protein Ligand Database (PLD): additional understanding of the nature and specificity of protein-ligand complexes.	Bioinform.	2003	DBLP DOI BibTeX RDF
26	Jorge Marcos, Jacobo Álvarez, Enrique Mandado, Andres Nogueiras	Failure Safe PLD Based Control System.	LATW	2001	DBLP BibTeX RDF
26	Sammy Cheung, Kar Keng Chua, Boon Jin Ang, Thow Pang Chong, Wei Lian Goay, Wei Yee Koay, Sin Wo Kuan, Chooi Pei Lim, Jiunn Shyong Oon, Theam Thye See, Chiakang Sung, Kim Pin Tan, Yu Fong Tan, Choong Kit Wong	A million gate PLD with 622 MHz I/O interface, multiple PLLs and high performance embedded CAM.	CICC	2000	DBLP DOI BibTeX RDF
26	Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello	A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming.	CICC	1999	DBLP DOI BibTeX RDF
26	Valeri Tomachev	The PLD-Implementation of Boolean Function Characterized by Minimum Delay.	FPL	1998	DBLP DOI BibTeX RDF
26	Schuyler Shimanek, Cesar Maldonado, Victor Ruybalid, Roy Darling	A low power, high performance, 960 macrocell, SRAM based complex PLD.	CICC	1998	DBLP DOI BibTeX RDF
26	Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner	A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability.	CICC	1998	DBLP DOI BibTeX RDF
26	John Turner, Richard Cliff, W. Leong, Cameron McClintock, Ninh Ngo, Khai Nguyen, Chiakang Sung, Bonnie Wang, J. Watson	Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process.	FPL	1995	DBLP DOI BibTeX RDF
26	Keith R. Dimond	An Automatic Technique for Realising User Interaction Processing in PLD Based Systems.	FPL	1995	DBLP DOI BibTeX RDF
26	Lech Józwiak, Frank Wolf	Efficient decomposition of assigned sequential machines and Boolean functions for PLD implementations.	Electronic Technology Directions	1995	DBLP DOI BibTeX RDF
26	Raja Venkateswaran, Pinaki Mazumder	A survey of DA techniques for PLD and FPGA based systems.	Integr.	1994	DBLP DOI BibTeX RDF
26	Om P. Agrawal	A High Density Complex PLD Family Optimized for Flexibility, Predictability and 100% Routability.	FPL	1994	DBLP DOI BibTeX RDF
26	Stanislaw Deniziak, Krzysztof Sapiecha	Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems.	ISCAS	1994	DBLP DOI BibTeX RDF
26	Steffen Becker 0002	Eine numerische Methode zur systematischen Analyse und Bewertung von PLD-Architekturen unter Nutzung der spezifischen Eigenschaften mit dem Ergebnis der Optimierung einer FPGA-Logikblockzelle.		1994	RDF
26	Luis Nozal, Santiago Lorenzo, Rui Boucho, Muzhir Shaban	Real time and low cost image processing architecture based on programmable logic devices (PLD).	IROS	1991	DBLP DOI BibTeX RDF
25	Manohar B. Srikanth, Hari Vasudevan, Manivannan Muniyandi	DC Motor Damping: A Strategy to Increase Passive Stiffness of Haptic Devices.	EuroHaptics	2008	DBLP DOI BibTeX RDF	Programmable logic devices (PLD), Haptics, Passiveness, Continuous Time, Instability
17	Abbas Nayebi, Hamid Sarbazi-Azad, Gunnar Karlsson	Routing, data gathering, and neighbor discovery in delay-tolerant wireless sensor networks.	IPDPS	2009	DBLP DOI BibTeX RDF
17	Issam W. Damaj	Higher-Level Hardware Synthesis of the KASUMI Algorithm.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	parallel algorithms, methodology, formal models, data encryption, gate array
17	Wenyi Feng, Jonathan W. Greene	Post-Placement Interconnect Entropy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
17	Kyungrae Cho, Sangtae Bae, Jahwan Koo, Jin-Wook Chung	On Achieving Proportional Loss Differentiation Using Dynamic-MQDDP with Differential Drop Probability.	HCI (8)	2007	DBLP DOI BibTeX RDF
17	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
17	Nursani Rahmatullah, Arif E. Nugroho	Hardware implementation of super minimum all digital FM demodulator.	ASP-DAC	2006	DBLP DOI BibTeX RDF
17	Jung Hwan Lee, Young-Don Ko, Min-Chang Jeong, Jae-Min Myoung, Ilgu Yun	PCA-Based Neural Network Modeling Using the Photoluminescence Data for Growth Rate of ZnO Thin Films Fabricated by Pulsed Laser Deposition.	ISNN (2)	2006	DBLP DOI BibTeX RDF
17	Tomasz Golonek, Damian Grzechca, Jerzy Rutkowski	Application of genetic programming to edge detector design.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Juan P. Oliver, Fiorella Haim, Sebastian Fernandez, Javier Rodriguez, Pablo Rolando	Hardware Lab at Home Possible with Ultra Low Cost Boards.	MSE	2005	DBLP DOI BibTeX RDF
17	Mike Hutton	Architecture and CAD for FPGAs.	SBCCI	2004	DBLP DOI BibTeX RDF
17	Christian Siemers, Volker Winterstein	Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
17	Kuen Hung Tsoi, Ka Hei Leung, Philip Heng Wai Leong	Compact FPGA-based True and Pseudo Random Number Generators.	FCCM	2003	DBLP DOI BibTeX RDF
17	Jouko Vankka, Jonne Lindeberg, Kari Halonen	Direct digital synthesizer with tunable delta sigma modulator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
17	Jouko Vankka, Jonne Lindeberg, Kari Halonen	Direct digital synthesizer with tunable phase and amplitude error feedback structures.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
17	Jouko Vankka, Jonne Lindeberg, Kari Halonen	FIR filters for compensating D/A converter frequency response distortion.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
17	Shahid Masud, John V. McCanny	Design of Silicon IP Cores for Biorthogonal Wavelet Transforms.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	rapid design, FPGA, synthesis, system-on-a-chip, dsp
17	Mark J. Boyd, Tracy Larrabee	A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems.	FCCM	2000	DBLP DOI BibTeX RDF
17	Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Tatsumi Furuya, Masaya Iwata, Tetsuya Higuchi	Hardware Evolution at Function Level.	PPSN	1996	DBLP DOI BibTeX RDF
17	Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou	BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.	DAC	1988	DBLP BibTeX RDF