Search results for "PowerPC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
134	Farooq Butt	Porting the mcc PowerPC C/C++ Compiler into an Interactive Development Environment.	ACM SIGPLAN Notices	1996	DBLP DOI BibTeX RDF	C++
101	Charles D. Norton	The International Workshop on Parallel C++ (IWPC++), Kanazawa, Ishikawa Prefecture, Japan.	ACM SIGPLAN Notices	1996	DBLP DOI BibTeX RDF	C++
85	Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden	Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.	DAC	1998	DBLP DOI BibTeX RDF	reliability, PowerPC, PowerPC, IR-drop, power distribution network
85	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
79	Brian F. Veale, John K. Antonio, Monte P. Tull, Sean A. Jones	Selection of instruction set extensions for an FPGA embedded processor core.	IPDPS	2006	DBLP DOI BibTeX RDF
76	Charles P. Roth, Frank E. Levine, Edward H. Welbon	Performance monitoring on the PowerPC 604 microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 604 microprocessor, multichip processors, Groupe Bull, performance evaluation, integrated circuit testing, workstations, performance monitoring, microprocessor chips, PCs, Microsoft, IBM, computer testing, Apple, Motorola
76	Carlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore	The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	PowerPC 603e microprocessor, low-power superscalar microprocessor, portable products, on-chip instruction, cache associativity, bus modes, 120 SPECint92, 105 SPECfp92, die size, software controllable power-down modes, power saving capability, 16 Kbyte, performance evaluation, performance, computer architecture, system design, power consumption, data cache, cache storage, microprocessor chips, frequency, system buses, portable computers, portable computers, transistors, 100 MHz
76	Trung A. Diep, Christopher Nelson, John Paul Shen	Performance Evaluation of the PowerPC 620 Microarchitecture.	ISCA	1995	DBLP DOI BibTeX RDF	PowerPC
68	Harold W. Cain, Kevin M. Lepak, Mikko H. Lipasti	A dynamic binary translation approach to architectural simulation.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
65	Peter M. Behr, S. Pletner, Angela C. Sodan	PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620.	HPCA	2000	DBLP DOI BibTeX RDF	PowerPC MPC620, two-way nodes, crossbar interconnection network, distributed memory architecture
65	Farooq Butt	Rapid Development of a Source-Level Debugger for PowerPC Microprocessors.	ACM SIGPLAN Notices	1994	DBLP DOI BibTeX RDF	PowerPC
55	Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi	Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Physical fault injection, Power supply disturbances, Concurrent error detection, Control flow checking
55	Mahdi Fazeli, Reza Farivar 0003, Seyed Ghassem Miremadi	A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.	DFT	2005	DBLP DOI BibTeX RDF
55	Patrick J. Bohrer, James L. Peterson, E. N. Elnozahy, Ramakrishnan Rajamony, Ahmed Gheith, Ronald L. Rockhold, Charles Lefurgy, Hazim Shafi, Tarun Nakra, Richard O. Simpson, Evan Speight, Kartik Sudeep, Eric Van Hensbergen, Lixin Zhang 0002	Mambo: a full system simulator for the PowerPC architecture.	SIGMETRICS Perform. Evaluation Rev.	2004	DBLP DOI BibTeX RDF
53	Allon Adir, Hagit Attiya, Gil Shurek	Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	PowerPC architecture, synchronization instructions, models, specification, consistency, Shared memory, multiprocessor systems, out-of-order execution
53	Shantanu Ganguly, Shervin Hojat	Clock distribution design and verification for PowerPC microprocessors.	ICCAD	1995	DBLP DOI BibTeX RDF	PowerPC
53	Julie Shipnes, Mike Philip	A Modular Approach to Motorola PowerPC Compilers.	Commun. ACM	1994	DBLP DOI BibTeX RDF	PowerPC
44	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
44	Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent	A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
44	Mario Porrmann, Ulrich Rückert 0001, Karl Michael Marks, Jörg Landmann	HiBRIC-MEM, a Memory Controller for PowerPC Based Systems.	EUROMICRO	1997	DBLP DOI BibTeX RDF
43	M. Armstead, Michael Cogswell, S. Halverson, T. Musta	PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine.	ICCD	1994	DBLP DOI BibTeX RDF
42	Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy	Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.	DAC	1998	DBLP DOI BibTeX RDF	PowerPC
42	Anthony Correale Jr.	Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers.	ISLPD	1995	DBLP DOI BibTeX RDF	PowerPC
34	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The Molen compiler for reconfigurable processors.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	FPGA, reconfigurable computing, Instruction scheduling
34	Pedro Trancoso	Dynamic Split: Flexible Border Between Instruction and Data Cache.	DSD	2005	DBLP DOI BibTeX RDF
34	Valentina Salapura, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, Dong Chen 0005, Paul Coteus, Alan Gara, Mark Giampapa, Michael Gschwind, Manish Gupta 0002, Shawn Hall, Ruud A. Haring, Philip Heidelberger, Dirk Hoenicke, Gerard V. Kopcsay, Martin Ohmacht, Rick A. Rand, Todd Takken, Pavlos Vranas	Power and performance optimization at the system level.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	BlueGene/L, application performance analysis, application scaling in multiprocessor systems, power/performance efficient systems, power/performance tradeos in systems, chip multiprocessors, supercomputers
34	Amir Hekmatpour, James Coulter	Coverage-Directed Management and Optimization of Random Functional Verification.	ITC	2003	DBLP DOI BibTeX RDF
34	Gordon J. Brebner	Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro.	FCCM	2002	DBLP DOI BibTeX RDF
34	Pedro Furtado 0001, Henrique Madeira	Fault Injection Evaluation of Assigned Signatures in a RISC Processor.	EDCC	1996	DBLP DOI BibTeX RDF
34	Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen	Can Trace-Driven Simulators Accurately Predict Superscalar Performance?	ICCD	1996	DBLP DOI BibTeX RDF
33	Magnus O. Myreen, Michael J. C. Gordon	Verified LISP Implementations on ARM, x86 and PowerPC.	TPHOLs	2009	DBLP DOI BibTeX RDF
33	Joon Huang Chuah, Joel Knight	VertiCal, a Universal Calibration System for eSys High Performance 32-Bit PowerPC Microcontrollers; Test Challenges & Solution.	DELTA	2006	DBLP DOI BibTeX RDF
33	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova	Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.	MTV	2005	DBLP DOI BibTeX RDF
33	Weining Gu, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Error Sensitivity of the Linux Kernel Executing on PowerPC G4 and Pentium 4 Processors.	DSN	2004	DBLP DOI BibTeX RDF
33	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	The PowerPC Backend Molen Compiler.	FPL	2004	DBLP DOI BibTeX RDF
33	Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina	Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.	ITC	2002	DBLP DOI BibTeX RDF
33	Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham	Validating PowerPC Microprocessor Custom Memories.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
33	Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina	At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.	VTS	2000	DBLP DOI BibTeX RDF	delay testing, at-speed testing, microprocessor testing
33	Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham	Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.	VTS	2000	DBLP DOI BibTeX RDF	Simulation, Validation, Memories, Assertions, Symbolic
33	Alan J. Drake, Todd D. Basso, Spencer M. Gold, Keith L. Kraver, Phiroze N. Parakh, Claude R. Gauthier, P. Sean Stetson, Richard B. Brown	CGaAs PowerPC FXU.	DAC	2000	DBLP DOI BibTeX RDF	design methodology, microprocessors, testing methodology, Gallium Arsenide
33	L. Robinson, G. Whisenhunt	A PowerPC platform full system simulation-from the MOOSE up.	IPCCC	1999	DBLP DOI BibTeX RDF
33	Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec	PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation.	Euro-Par	1999	DBLP DOI BibTeX RDF
33	Li-C. Wang, Magdy S. Abadir, Jing Zeng	On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	assertion test generation, design error model, validation, ATPG, logic verification, symbolic trajectory evaluation
33	Li-C. Wang, Magdy S. Abadir, Jing Zeng	Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.	DATE	1998	DBLP DOI BibTeX RDF	Design Error Models, Verification, Design Validation
33	Rajesh Raina, Robert F. Molyneaux	Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	High-Level Design Validation, Silicon Validation, Pseudo-Random Testing, Microprocessor Testing
33	Craig Hunter, Justin Gaither	Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core.	ITC	1998	DBLP DOI BibTeX RDF
33	Lucas Aaron Womack	A Study of Virtual Memory MTU Reassembly within the PowerPC Architectur.	MASCOTS	1997	DBLP DOI BibTeX RDF
33	Sonya Gary, Pete Ippolito, Gianfranco Gerosa, Carl Dietz, Jim Eno, Hector Sanchez	PowerPC 603, A Microprocessor for Portable Computers.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
32	Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose	Performance and power evaluation of an in-line accelerator.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	vmx, accelerator, powerpc, simd
32	Joe Gebis, David A. Patterson 0001	Embracing and Extending 20th-Century Instruction Set Architectures.	Computer	2007	DBLP DOI BibTeX RDF	instruction set architectures, PowerPC, SIMD processors, vector architecture
32	Jeff H. Derby, Robert K. Montoye, José E. Moreira	VICTORIA: VMX indirect compute technology oriented towards in-line acceleration.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	VMX, SIMD, accelerators, powerPC
32	Kazunori Ogata, Hideaki Komatsu, Toshio Nakatani	Bytecode fetch optimization for a Java interpreter.	ASPLOS	2002	DBLP DOI BibTeX RDF	pipelined interpreter, stack caching, Java, performance, superscalar processor, PowerPC, bytecode interpreter
32	Dean E. Dauger, Viktor K. Decyk	Numerically-Intensive "Plug-and-Play" Parallel Computing.	CLUSTER	2001	DBLP DOI BibTeX RDF	AppleSeed, plug and play, MacMPI, Pooch, easy, parallel computing, GUI, MPI, cluster computing, Unix, technology transfer, Macintosh, PowerPC, ease of use, Apple, Mac, plasma physics, AltiVec
32	Yossi Malka, Avi Ziv	Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha
32	Thomas H. Einstein	Mercury Computer Systems' modular heterogeneous RACE(R) multicomputer.	Heterogeneous Computing Workshop	1997	DBLP DOI BibTeX RDF	Mercury Computer Systems, modular heterogeneous RACE multicomputer, heterogeneous multicomputer, Analog Devices, SHARC 21060, Apple PowerPC 603p, optimal processor, physical processing density, heterogeneity, distributed memory systems, programmability, IBM, hardware cost, Motorola
32	Bruce L. Jacob, Trevor N. Mudge	Software-Managed Address Translation.	HPCA	1997	DBLP DOI BibTeX RDF	software-managed address translation, memory management design, high clock-rate PowerPC implementation, OSF/1, superpages, sub-page protection, sparse address spaces, shared memory, storage management, Mach
32	Chi-Hung Chi, Siu-Chung Lau	Reducing data access penalty using intelligent opcode-driven cache prefetching.	ICCD	1995	DBLP DOI BibTeX RDF	data access penalty, intelligent opcode-driven, LOAD-UPDATE, LOAD-MODIFY, IBM PowerPC, HP Precision Architecture, intelligent data prefetching, instruction decode unit, storage management, data cache, cache storage, cache prefetching
23	Manoel T. F. Cunha, Jose C. F. Telles, Alvaro L. G. A. Coutinho	On the Implementation of Boundary Element Engineering Codes on the Cell Broadband Engine.	VECPAR	2008	DBLP DOI BibTeX RDF	Parallel Programming, SIMD, Vectorization, Cell Broadband Engine, Boundary Element Method, Boundary Elements
23	Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani	AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors.	PACT	2007	DBLP DOI BibTeX RDF
23	Sándor Héman, Niels Nes, Marcin Zukowski, Peter A. Boncz	Vectorized data processing on the cell broadband engine.	DaMoN	2007	DBLP DOI BibTeX RDF
23	Marc Berndl, Benjamin Vitale, Mathew Zaleski, Angela Demke Brown	Context Threading: A Flexible and Efficient Dispatch Technique for Virtual Machine Interpreters.	CGO	2005	DBLP DOI BibTeX RDF
23	Akihiko Miyoshi, Charles Lefurgy, Eric Van Hensbergen, Ramakrishnan Rajamony, Raj Rajkumar	Critical power slope: understanding the runtime effects of frequency scaling.	ICS	2002	DBLP DOI BibTeX RDF	energy aware computing
23	M. D. Bennett, Neil C. Audsley	Predictable and Efficient Virtual Addressing for Safety-Critical Real-Time Systems.	ECRTS	2001	DBLP DOI BibTeX RDF
23	Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons	Register-sensitive selection, duplication, and sequencing of instructions.	ICS	2001	DBLP DOI BibTeX RDF
23	Li-C. Wang, Magdy S. Abadir	On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	custom circuits, high level circuit extraction, ATPG, DFT, time-to-market
23	Li-C. Wang, Magdy S. Abadir	Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	assertion test generation, assertion, array, design error, logic verification, symbolic trajectory evaluation
23	Armin Biere, Edmund M. Clarke, Richard Raimi, Yunshan Zhu	Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs.	CAV	1999	DBLP DOI BibTeX RDF
23	Esther Stümpel, Michael Thies, Uwe Kastens	VLIW Compilation Techniques for Superscalar Architectures.	CC	1998	DBLP DOI BibTeX RDF
23	E. Kofi Vida-Torku, George Joos	Designing for scan test of high performance embedded memories.	ITC	1998	DBLP DOI BibTeX RDF
22	Kun Cheng, Weiyue Liu, Qi Shen, Shengkai Liao	Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC.	CoRR	2018	DBLP BibTeX RDF
22	Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li	Erratum to: XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
22	Rui Zhou 0005, Qingguo Zhou, Yong Sheng, Kuan-Ching Li	XtratuM/PPC: a hypervisor for partitioned system on PowerPC processors.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
22	Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes	Optimizing the performance of streaming numerical kernels on the IBM Blue Gene/P PowerPC 450 processor.	Int. J. High Perform. Comput. Appl.	2013	DBLP DOI BibTeX RDF
22	Radisav Cojbasic, Omer Cogal, Pascal Andreas Meinerzhagen, Christian Senning, Conor Slater, Thomas Maeder, Andreas Burg, Yusuf Leblebici	FireBird: PowerPC e200 based SoC for high temperature operation.	CICC	2013	DBLP DOI BibTeX RDF
22	Tareq M. Malas, Aron J. Ahmadia, Jed Brown, John A. Gunnels, David E. Keyes	Optimizing the Performance of Streaming Numerical Kernels on the IBM Blue Gene/P PowerPC 450 Processor	CoRR	2012	DBLP BibTeX RDF
22		IBM PowerPC.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
22	Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French	The PowerPC 405 Memory Sentinel and Injection System.	FCCM	2011	DBLP DOI BibTeX RDF
22	Rod Blaine Foist, Cristian Grecu, André Ivanov, Robin Turner	An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.	IEEE Trans. Educ.	2008	DBLP DOI BibTeX RDF
22	Rod Blaine Foist, André Ivanov, Robin Turner	An FPGA Design Project: Creating a PowerPC Subsystem Plus User Logic.	MSE	2007	DBLP DOI BibTeX RDF
22	Stephen Barrett, Julie Spratt, Ralph Depping, Ramachandran Ranganathan	PowerPC Kernel Implementation for GSM Radio Platform.	ESA	2007	DBLP BibTeX RDF
22	Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai	Automatic testcase synthesis and performance model validation for high performance PowerPC processors.	ISPASS	2006	DBLP DOI BibTeX RDF
22	Arvind	UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures.	VLSI Design	2006	DBLP DOI BibTeX RDF
22	Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin	Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.	Des. Autom. Embed. Syst.	2005	DBLP DOI BibTeX RDF
22	Charles D. Wait	IBM PowerPC 440 FPU with complex-arithmetic extensions.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
22	Himyanshu Anand, Jayanta Bhadra, Alper Sen 0001, Magdy S. Abadir, Kenneth G. Davis	Establishing latch correspondence for embedded circuits of PowerPC microprocessors.	HLDVT	2005	DBLP DOI BibTeX RDF
22	Waleed Al-Assadi, Thomas Dick	Design for Test Methodology for the IBM PowerPC 440 Embedded Core.	CDES	2005	DBLP BibTeX RDF
22	Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman	Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.	ISQED	2005	DBLP DOI BibTeX RDF
22	Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan	Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture.	ITC	2005	DBLP DOI BibTeX RDF
22	Gerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris	A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist.	SoCC	2004	DBLP DOI BibTeX RDF
22		Micro News: Moving into the 90-nm chip market; PowerPC runs at up to 2.5 GHz.	IEEE Micro	2003	DBLP DOI BibTeX RDF
22	Kevin J. Nowka, Gary D. Carpenter, Bishop Brock	The design and application of the PowerPC 405LP energy-efficient system-on-a-chip.	IBM J. Res. Dev.	2003	DBLP DOI BibTeX RDF
22	Hazim Shafi, Patrick J. Bohrer, James Phelan, Cosmin Rusu, James L. Peterson	Design and validation of a performance and power simulator for PowerPC systems.	IBM J. Res. Dev.	2003	DBLP DOI BibTeX RDF
22	Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns	A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
22	Richard Raimi, James Lear	Silicon Debug of a PowerPC[tm] Microprocessor Using Model Checking.	Formal Methods Syst. Des.	2002	DBLP DOI BibTeX RDF
22	Daniel Grieg, Cedric Collins, Troy Benjegerdes, Brett M. Bode	Linux Clustering using the PowerPC G4 Processor.	IASTED PDCS	2002	DBLP BibTeX RDF
22	Paul Kartschoke, Shervin Hojat	Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor.	ISQED	2001	DBLP DOI BibTeX RDF
22	Gilbert Vandling	Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo.	ITC	2001	DBLP DOI BibTeX RDF
22	Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales	AltiVec Extension to PowerPC Accelerates Media Processing.	IEEE Micro	2000	DBLP DOI BibTeX RDF
22	Frank P. O'Connell, Steven W. White	POWER3: The next generation of PowerPC processors.	IBM J. Res. Dev.	2000	DBLP DOI BibTeX RDF
22	John M. Borkenhagen, Richard J. Eickemeyer, Ronald N. Kalla, Steven R. Kunkel	A multithreaded PowerPC processor for commercial servers.	IBM J. Res. Dev.	2000	DBLP DOI BibTeX RDF