Search results for "QDI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.	CHES	2006	DBLP DOI BibTeX RDF	QDI Asynchronous circuits, Path Swapping (PS), Power analysis
90	Recep O. Ozdag, Peter A. Beerel	High-Speed QDI Asynchronous Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks
77	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
60	Mehrdad Najibi, Kamran Saleh, Hossein Pedram	Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	quasi-delay insensitive, standard-cell layout, asynchronous circuits
60	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Automatic Generation of 1-of-M QDI Asynchronous Adders.	SBCCI	2003	DBLP DOI BibTeX RDF
52	Charlie Brej, Doug Edwards	Forward and backward guarding in early output logic.	DDECS	2009	DBLP DOI BibTeX RDF
52	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
52	Yannick Monnet, Marc Renaudin, Régis Leveugle	Hardening Techniques against Transient Faults for Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
52	Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel	An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
49	Anh-Vu Dinh-Duc	Synthèse automatique de circuits asynchrones QDI. (Automatic synthesis of QDI asynchronous circuits).		2003	RDF
48	Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky	An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.	ACSD	2005	DBLP DOI BibTeX RDF	asynchronous EDA, QDI, synthesis, ASIC, HDL
42	Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram	A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits.	PATMOS	2007	DBLP DOI BibTeX RDF
42	Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram	A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
42	Eslam Yahya, Marc Renaudin	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
42	Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Statistic Implementation of QDI Asynchronous Primitives.	PATMOS	2003	DBLP DOI BibTeX RDF
35	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
35	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
35	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous circuits transient faults sensitivity evaluation.	DAC	2005	DBLP DOI BibTeX RDF	quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
35	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.	PATMOS	2003	DBLP DOI BibTeX RDF
35	Nattha Sretasereekul, Takashi Nanya	Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits.	ASP-DAC	2001	DBLP DOI BibTeX RDF
29	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
25	Raghda El Shehaby, Matthias Függer, Andreas Steininger	On the Susceptibility of QDI Circuits to Transient Faults.	CoRR	2023	DBLP DOI BibTeX RDF
25	Shahzad Haider, Song Chen 0001	Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches.	MWSCAS	2023	DBLP DOI BibTeX RDF
25	Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné	A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries.	ASYNC	2023	DBLP DOI BibTeX RDF
25	Shahzad Haider, Junhao Liang, Song Chen 0001	Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems.	NEWCAS	2023	DBLP DOI BibTeX RDF
25	Shahzad Haider, Ke Hu, Song Chen 0001	Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch.	SOCC	2023	DBLP DOI BibTeX RDF
25	Raghda El Shehaby, Matthias Függer, Andreas Steininger	On the Susceptibility of QDI Circuits to Transient Faults.	FORMATS	2023	DBLP DOI BibTeX RDF
25	Zaheer Tabassam, Andreas Steininger	Towards Resilient QDI Pipeline Implementations.	DSD	2022	DBLP DOI BibTeX RDF
25	Gabriel C. Duarte, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista	Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA.	LASCAS	2022	DBLP DOI BibTeX RDF
25	Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans	Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers.	ISCAS	2022	DBLP DOI BibTeX RDF
25	Raghda El Shehaby, Andreas Steininger	Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults.	DFT	2022	DBLP DOI BibTeX RDF
25	Zaheer Tabassam, Andreas Steininger	SET Hardened Derivatives of QDI Buffer Template.	DFT	2022	DBLP DOI BibTeX RDF
25	Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam	Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.	ASYNC	2021	DBLP DOI BibTeX RDF
25	Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista	A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication.	LASCAS	2021	DBLP DOI BibTeX RDF
25	Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang	A fully asynchronous QDI mesh router based on 28nm standard cells.	ASICON	2021	DBLP DOI BibTeX RDF
25	Thomas R. Barrick, Catherine A. Spilling, Carson Ingo, Jeremy Madigan, Jeremy D. Isaacs, Philip Rich, Timothy L. Jones, Richard L. Magin, Matt G. Hall, Franklyn A. Howe	Quasi-diffusion magnetic resonance imaging (QDI): A fast, high b-value diffusion imaging technique.	NeuroImage	2020	DBLP DOI BibTeX RDF
25	Matheus Trevisan Moreira, Stefano Giaconi	Chronos Link: A QDI Interconnect for Modern SoCs.	ASYNC	2020	DBLP DOI BibTeX RDF
25	Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans	A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow.	ASYNC	2020	DBLP DOI BibTeX RDF
25	Duarte Lopes de Oliveira, Gabriel C. Duarte, Nicolly N. M. Cardoso, Gracieth Cavalcanti Batista	Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools.	SBCCI	2020	DBLP DOI BibTeX RDF
25	Raghda El Shehaby, Andreas Steininger	On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective.	ICCD	2020	DBLP DOI BibTeX RDF
25	Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans	Leveraging QDI Robustness to Simplify the Design of IoT Circuits.	ISCAS	2020	DBLP DOI BibTeX RDF
25	Ghania Ait Abdelmalek, Rezki Ziani, Rabah Mokdad	Security and fault tolerance evaluation of TMR-QDI circuits.	IET Inf. Secur.	2019	DBLP DOI BibTeX RDF
25	Ned Bingham, Rajit Manohar	QDI Constant-Time Counters.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
25	Jean-Philippe Georges	Performance evaluation & network automation. For a triptych QoS, QoE, QiS. (Évaluation de performances & automatisation de réseaux. Pour un triptyque QdS, QdE, QdI).		2019	RDF
25	Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans	Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools.	ASYNC	2019	DBLP DOI BibTeX RDF
25	Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang	Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
25	Kwen-Siong Chong, Weng-Geng Ho, Tong Lin 0001, Bah-Hwee Gwee, Joseph S. Chang	Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
25	Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel	Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
25	Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans	A comparison of asynchronous QDI templates using static logic.	LASCAS	2017	DBLP DOI BibTeX RDF
25	James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee	DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.	ISCAS	2017	DBLP DOI BibTeX RDF
25	Syed Rafay Hasan, Waqas Gul, Osman Hasan	Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous.	Integr.	2016	DBLP DOI BibTeX RDF
25	Benjamin Z. Tang, Frank Lane	Low Power QDI Asynchronous FFT.	ASYNC	2016	DBLP DOI BibTeX RDF
25	Weng-Geng Ho, Nan Liu 0002, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.	ISCAS	2016	DBLP DOI BibTeX RDF
25	Waqas Gul, Syed Rafay Hasan, Osman Hasan, Faiq Khalid Lodhi, Falah R. Awwad	Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces.	ISCAS	2016	DBLP DOI BibTeX RDF
25	Weng-Geng Ho, Ali Akbar Pammu, Nan Liu 0002, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee	Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.	ISIC	2016	DBLP DOI BibTeX RDF
25	Sean Keller, Alain J. Martin, Chris Moore	DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS.	ASYNC	2015	DBLP DOI BibTeX RDF
25	Bo-Yuan Huang 0001, Yi-Hsiang Lai, Jie-Hong Roland Jiang	Asynchronous QDI Circuit Synthesis from Signal Transition Protocols.	ICCAD	2015	DBLP DOI BibTeX RDF
25	Fu-Chiung Cheng, An-Hao Peng, Xiao-Li Lin, Shu-Chuan Huang	Hybrid encoded QDI combinational circuits.	NEWCAS	2015	DBLP DOI BibTeX RDF
25	Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar	Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications.	ISCAS	2015	DBLP DOI BibTeX RDF
25	Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang 0003	Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
25	Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
25	Matheus T. Moreira, Ney Laert Vilar Calazans	Advances on the state of the art in QDI design.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
25	Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel	Reconditioning: Automatic Power Optimization of QDI Circuits.	ASYNC	2014	DBLP DOI BibTeX RDF
25	Fu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang, Ching-Yang Huang	Synthesis of QDI FSMs from Synchronous Specifications.	ASYNC	2014	DBLP DOI BibTeX RDF
25	Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho	Synthesis of asynchronous QDI circuits using synchronous coding specifications.	ISCAS	2014	DBLP DOI BibTeX RDF
25	Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans	Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis.	ACM Great Lakes Symposium on VLSI	2014	DBLP DOI BibTeX RDF
25	Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans	Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design.	ISQED	2014	DBLP DOI BibTeX RDF
25	Masashi Imai, Tomohiro Yoneda	Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits.	APCCAS	2014	DBLP DOI BibTeX RDF
25	Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang 0003	Transient Fault Tolerant QDI Interconnects Using Redundant Check Code.	DSD	2013	DBLP DOI BibTeX RDF
25	Jérémie Hamon, Edith Beigné	Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology.	ASYNC	2013	DBLP DOI BibTeX RDF
25	Fu-Chiung Cheng, Chi Chen	Can QDI Combinational Circuits be Implemented without C-elements?	ASYNC	2013	DBLP DOI BibTeX RDF
25	Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.	ISCAS	2013	DBLP DOI BibTeX RDF
25	Yvain Thonnart, Edith Beigné, Pascal Vivet	A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits.	ASYNC	2012	DBLP DOI BibTeX RDF
25	Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha	A Digital Neurosynaptic Core Using Event-Driven QDI Circuits.	ASYNC	2012	DBLP DOI BibTeX RDF
25	Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans	Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes.	SBCCI	2012	DBLP DOI BibTeX RDF
25	Nilanka T. Rajapaksha, Arjuna Madanayake	Asynchronous-QDI 2D IIR digital filter circuits.	ISCAS	2011	DBLP DOI BibTeX RDF
25	Werner Friesenbichler, Thomas Panhofer, Andreas Steininger	A deterministic approach for hardware fault injection in asynchronous QDI logic.	DDECS	2010	DBLP DOI BibTeX RDF
25	Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet	RAT-based formal verification of QDI asynchronous controllers.	FDL	2009	DBLP BibTeX RDF
25	Ali-Asghar Salehpour, Masoud Zamani, Amir-Mohammad Rahmani, Siamak Mohammadi, Hossein Pedram, Mohammadreza Binesh Marvasti	A novel test environment for template based QDI asynchronous circuits.	ICECS	2008	DBLP DOI BibTeX RDF
25	J. Fragoso, Gilles Sicard, Marc Renaudin	Estimation rapide du couple énergie/délai des circuits asynchrones QDI.	Tech. Sci. Informatiques	2007	DBLP DOI BibTeX RDF
25	Recep O. Ozdag, Peter A. Beerel	An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
25	Recep O. Ozdag, Peter A. Beerel	A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates.	ASYNC	2004	DBLP DOI BibTeX RDF
25	Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin	Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.	IWLS	2002	DBLP BibTeX RDF
17	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	A comprehensive approach for soft error tolerant Four State Logic.	DDECS	2009	DBLP DOI BibTeX RDF
17	Gang Jin, Lei Wang 0011, Zhiying Wang	The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.	NAS	2009	DBLP DOI BibTeX RDF
17	Werner Friesenbichler, Thomas Panhofer, Martin Delvai	Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
17	Behnam Ghavami, Hossein Pedram	An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips.	PATMOS	2007	DBLP DOI BibTeX RDF
17	Yannick Monnet, Marc Renaudin, Régis Leveugle	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.	IOLTS	2007	DBLP DOI BibTeX RDF
17	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
17	Alain J. Martin	Can Asynchronous Techniques Help the SoC Designer?	VLSI-SoC	2006	DBLP DOI BibTeX RDF
17	Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach	A DFT Architecture for Asynchronous Networks-on-Chip.	ETS	2006	DBLP DOI BibTeX RDF
17	Yong Xiao, Runde Zhou	Single-track asynchronous pipeline controller design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar	Asynchronous gate-diffusion-input (GDI) circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
17	Mohammad K. Akbari, Ali Jahanian 0001, Mohsen Naderi, Bahman Javadi	Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.	DSD	2004	DBLP DOI BibTeX RDF
17	David Fang, Rajit Manohar	Non-Uniform Access Asynchronous Register Files.	ASYNC	2004	DBLP DOI BibTeX RDF
17	Mika Nyström, Elaine Ou, Alain J. Martin	An Eight-Bit Divider Implemented in Asynchronous Pulse Logic.	ASYNC	2004	DBLP DOI BibTeX RDF
17	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous Circuits Sensitivity to Fault Injection.	IOLTS	2004	DBLP DOI BibTeX RDF
17	Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari	An Asynchronous Viterbi Decoder for Low-Power Applications.	PATMOS	2003	DBLP DOI BibTeX RDF
17	Paul I. Pénzes, Alain J. Martin	An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.	DATE	2002	DBLP DOI BibTeX RDF
17	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design