Search results for "Radix-2"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Tomás Lang, Alberto Nannarelli	A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	decimal division, algorithms and architectures for floating-point arithmetic, Decimal arithmetic, digit-recurrence division
72	Shuenn-Yuh Lee, Chia-Chyang Chen	VLSI implementation of programmable FFT architectures for OFDM communication system.	IWCMC	2006	DBLP DOI BibTeX RDF	FFT processor, low power, VLSI architecture
72	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A split-radix algorithm for 2-D DFT.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
63	Pere Martí-Puig, Ramón Reig Bolaño, Vicenç Parisi Baradad	Radix-R FFT and IFFT Factorizations for Parallel Implementation.	DCAI	2008	DBLP DOI BibTeX RDF	Parallel algorithms, Fast Fourier Transform, Fast algorithms
63	Jin-Hua Hong, Cheng-Wen Wu	Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
63	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An efficient split-radix FFT algorithm.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
63	Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera	Radix-4 Vectoring CORDIC Algorithm and Architectures.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
61	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
55	J. Arjun Prabhu, Gregory B. Zyner	167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
54	Shuenn-Yuh Lee, Chia-Chyang Chen, Shyh-Chyang Lee, Chih-Jen Cheng	A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
54	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
54	Miriam Leeser, John W. O'Leary	Verification of a subtractive radix-2 square root algorithm and implementation.	ICCD	1995	DBLP DOI BibTeX RDF	subtractive radix-2 square root, floating point square root hardware, Intel Pentium, radix-2 square root, MIPS R4400, RTL level, verification, formal verification, theorem proving, theorem proving, floating point arithmetic, optimizing transformations
47	Daisuke Takahashi, Yasumasa Kanada	High-Performance Radix-2, 3 and 5 Parallel 1-D Complex FFT Algorithms for Distributed-Memory Parallel Computers.	J. Supercomput.	2000	DBLP DOI BibTeX RDF	3 and 5, cyclic distribution, fast Fourier transform, all-to-all communication, distributed-memory parallel computer, radix-2
47	Hosahalli R. Srinivas, Keshab K. Parhi	A floating point radix 2 shared division/square root chip.	ICCD	1995	DBLP DOI BibTeX RDF	floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm
46	Ioannis Kouretas, Vassilis Paliouras	Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication.	PATMOS	2008	DBLP DOI BibTeX RDF
45	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	A General Class of Split-Radix FFT Algorithms for the Computation of the DFT of Length-2m.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
45	Bryan Catanzaro, Brent E. Nelson	Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
45	Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata	Cordic based parallel/pipelined architecture for the Hough transform.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
45	Luis A. Montalvo, Alain Guyot	Svoboda-Tung division with no compensation.	VLSI Design	1995	DBLP DOI BibTeX RDF	Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits
43	T. C. Choinski, T. T. Tylaska	Generation of Digit Reversed Address Sequences for Fast Fourier Transforms.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	digit reversed address sequences generation, radix-4, binary counter, address sequences, fast Fourier transforms, fast Fourier transforms, hardware design, computerised signal processing, radix-2
38	Jae-Hee Won, Kiyoung Choi	Low power self-timed Radix-2 division (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	RSD, radix-2 division, low power, self-timed
37	Jean-Luc Beuchat, Jean-Michel Muller	Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement.	ASAP	2005	DBLP DOI BibTeX RDF
36	Satyendra R. Datla, Mitchell A. Thornton, David W. Matula	A Low Power High Performance Radix-4 Approximate Squaring Circuit.	ASAP	2009	DBLP DOI BibTeX RDF
36	Shuenn-Shyang Wang, Chien-Sung Li	An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	variable length FFT, substructure sharing, Fast Fourier Transform, OFDM
36	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	Design of a multidimensional split vector-radix decimation-in-frequency FFT algorithm.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Peter-Michael Seidel, Lee D. McFearin, David W. Matula	Secondary Radix Recodings for Higher Radix Multipliers.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication
36	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An efficient split-radix FHT algorithm.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
36	Behrooz Parhami	Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division
36	Jaehyun Baek, Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Seung Keun Oh	A continuous flow mixed-radix FFT architecture with an in-place algorithm.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
36	Alexandre F. Tenca, Georgi Todorov, Çetin Kaya Koç	High-Radix Design of a Scalable Modular Multiplier.	CHES	2001	DBLP DOI BibTeX RDF	modular multiplier, montgomery multiplier, high-radix, scalable architecture
36	Alexandre F. Tenca, Milos D. Ercegovac	On the Design of High-Radix On-Line Division for Long Precision.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
36	Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata	High Radix Cordic Rotation Based on Selection by Rounding.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF	Rotation mode, High radix algorithm, CORDIC algorithm
36	Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera	Radix-4 Vectoring Cordic Algorithm And Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures
36	Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Redundant CORDIC Rotator Based on Parallel Prediction.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	High speed processor, Parallel prediction, Parallel architecture, CORDIC algorithm, Redundant arithmetic
33	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
32	Nan Jiang 0009, David Money Harris	Parallelized radix-2 scalable Montgomery multiplier.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
32	Alexander A. Petrovsky, Sergei L. Shkredov	Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations.	PARELEC	2006	DBLP DOI BibTeX RDF
32	Kooroush Manochehri, Saadat Pourmozafari	Modified Radix-2 Montgomery Modular Multiplication to Make It Faster and Simpler.	ITCC (1)	2005	DBLP DOI BibTeX RDF	Radix2, Exponentiation, Modular multiplication, Montgomery, CSA
29	Gautam Abhaychand Shah, Tejmal Saubhagyamal Rathore	A New Fast Radix-2 Decimation-in-Frequency Algorithm for Computing the Discrete Hartley Transform.	CICSyN	2009	DBLP DOI BibTeX RDF	decimation-in-frequency, discrete Hartley transform, matrix approach, algorithm, radix-2
29	Mahn-ling Woo, Rosemary A. Renaut	Unordered parallel distance-1 and distance-2 FFT algorithms of radix 2 and (4-2).	SAC	1994	DBLP DOI BibTeX RDF	mixed-radix (4-2) FFT, parallel FFT algorithms, radix-2 FFT, complexity analysis
29	Shalhav Zohar	Rounding and Truncation in Radix (-2) Systems.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	N-bit rounding algorithms, radix (-2), rounding error bounds, truncation errors
29	Paul W. Baker	More Efficient Radix-2 Algorithms for Some Elementary Functions.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	variable left shift, Digital arithmetic, iterative algorithms, elementary functions, radix 2
28	Renato H. Neuenfeld, Mateus Beck Fonseca, Eduardo A. C. da Costa, Jean P. Oses	Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies.	LASCAS	2017	DBLP DOI BibTeX RDF
28	Zhuo Qian, Martin Margala	Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
28	Renato Neuenfeld, Mateus Fonseca, Eduardo A. C. da Costa	Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time.	LASCAS	2016	DBLP DOI BibTeX RDF
28	Manzur Rahman, Arindam Sanyal, Nan Sun 0001	A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
28	Andrew Carter, Paula Ning, William Koven, David Money Harris, Michael Braly, Nathan Jones, Julien Massas, Trevin Murakami, Alexandra Simoni, Sanu Mathew	Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers.	ACSSC	2013	DBLP DOI BibTeX RDF
28	Waqar Hussain 0001, Fabio Garzia, Jari Nurmi	Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platform.	DDECS	2010	DBLP DOI BibTeX RDF
28	Peter Westermann, Hartmut Schröder	Constraints on the SIMD vectorization of radix-2 and mixed-radix FFTS.	EUSIPCO	2009	DBLP BibTeX RDF
28	Saad Bouguezel, M. Omair Ahmad, M. N. Shanmukha Swamy	New radix-(2×2×2)/(4×4×4) and radix-(2×2×2)/(8×8×8) DIF FFT algorithms for 3-D DFT.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
28	Alexander A. Petrovsky, Sergei L. Shkredov	Radix 2 and split radix 2-4 algorithms in formal synthesis of parallel-pipeline FFT processors.	EUSIPCO	2004	DBLP BibTeX RDF
28	Chitlur Nagabhushan, Olga Kosheleva, Sergio D. Cabrera, Glenn A. Gibson	Design of Radix-2 and Radix-4 FFT Processors Using a Modular Architecture Family.	PDPTA	1996	DBLP BibTeX RDF
27	Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi	An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm.	Public Key Cryptography	2008	DBLP DOI BibTeX RDF	MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
27	Zhongfeng Wang 0001	High-Speed Recursion Architectures for MAP-Based Turbo Decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Y. Wang, Y. Tang, Y. Jiang, Y.-G. Chung, S.-S. Song, M.-S. Lim	Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
27	Shengmei Mou, Xiaodong Yang 0002	Research on the RAW Dependency in Floating-point FFT Processors.	SNPD (1)	2007	DBLP DOI BibTeX RDF
27	Sylvie Boldo	Pitfalls of a Full Floating-Point Proof: Example on the Formal Proof of the Veltkamp/Dekker Algorithms.	IJCAR	2006	DBLP DOI BibTeX RDF
27	Zhongjun Wang, Lee Guek Yeo, Wenzhen Li, Yanxin Yan, Yujing Ting, Masayuki Tomisawa	A Novel FFT Processor for OFDM UWB Systems.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	Efficient output-pruning of the 2-D FFT algorithm.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
27	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	High-Radix Logarithm with Selection by Rounding.	ASAP	2002	DBLP DOI BibTeX RDF
27	Che-Han Wu, Ming-Der Shieh, Chien-Hsing Wu 0002, Ming-Hwa Sheu, Jia-Lin Sheu	A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
27	Stuart F. Oberman, Michael J. Flynn	Minimizing the complexity of SRT tables.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
27	M. C. Mekhallalati, Ahmed S. Ashur, M. K. Ibrahim	Novel Radix Finite Field Multiplier for GF(2m).	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
27	Francisco Argüello, Emilio L. Zapata	Constant geometry split-radix algorithms.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
27	Chung Nan Lyu, David W. Matula	Redundant Binary Booth Recoding.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
27	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Digit On-line Large Radix CORDIC Rotator.	ASAP	1995	DBLP DOI BibTeX RDF	Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm
27	Stephen E. McQuillan, John V. McCanny	Fast VLSI algorithms for division and square root.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
24	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
24	Jarmo Takala, Konsta Punkka	Scalable FFT Processors and Pipelined Butterfly Units.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	parallel processing, application-specific integrated circuit, CORDIC, distributed arithmetic, radix-2
24	Syed Mahfuzul Aziz, S. J. Carr	On C-Testability of Carry Free Dividers.	DELTA	2002	DBLP DOI BibTeX RDF	Carry-free, C-Testability, Divider, Radix-2
24	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
24	Lutz J. Micheel, Hans L. Hartnagel	Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation.	ISMVL	1996	DBLP DOI BibTeX RDF	heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
24	Ryutaro Murakami, Yoshiteru Ohkura, Ryosaku Shimada	2k-ary Cyclic AN Codes for Burst Error Correction.	ISMVL	1995	DBLP DOI BibTeX RDF	2/sup k/-ary cyclic AN codes, burst error correction, radix 2/sup k/ expressions, code structure, arithmetic burst errors, burst error correction ability, binary cyclic AN code, error correction codes, error detection, error detection codes, arithmetic codes, arithmetic operations, cyclic codes
23	Alex Piñeiro, Javier D. Bruguera, Fabrizio Lamberti, Paolo Montuschi	A Radix-2 Digit-by-Digit Architecture for Cube Root.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cost/performance, High-Speed Arithmetic
23	Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine.	ICCD	2007	DBLP DOI BibTeX RDF
23	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
23	Andreas Lindahl, Lars Bengtsson	A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.	DSD	2005	DBLP DOI BibTeX RDF
23	David Money Harris, Ram Krishnamurthy 0001, Mark A. Anders 0001, Sanu Mathew, Steven Hsu	An Improved Unified Scalable Radix-2 Montgomery Multiplier.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
23	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An approach for computing the radix-2/4 DIT FHT and FFT algorithms using a unified structure.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
23	Hosahalli R. Srinivas, Keshab K. Parhi	A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
23	Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto	30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	simulation, CMOS, division, square root, self-timed, SRT, on-the-fly
18	Clemens Heuberger, James A. Muir	Unbalanced digit sets and the closest choice strategy for minimal weight integer representations.	Des. Codes Cryptogr.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 11A63, 94A60, 68W40
18	Markus Püschel, Martin Rötteler	Algebraic signal processing theory: Cooley-Tukey type algorithms on the 2-D hexagonal spatial lattice.	Appl. Algebra Eng. Commun. Comput.	2008	DBLP DOI BibTeX RDF
18	Paolo Montuschi, Javier D. Bruguera, Luigi Ciminiera, José-Alejandro Piñeiro	A Digit-by-Digit Algorithm for mth Root Extraction.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	integer rooting, digit-by-digit algorithms, higher radix, computer arithmetic
18	Yingtuo Ju, Guoan Bi	Generalized Fast Algorithms for the Polynomial Time-Frequency Transform.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
18	Soo-Chang Pei, Kuo-Wei Chang	Efficient Bit and Digital Reversal Algorithm Using Vector Calculation.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
18	Nathaniel Ross Pinckney, David Money Harris	Parallelized radix-4 scalable montgomery multipliers.	SBCCI	2007	DBLP DOI BibTeX RDF	cryptography, RSA, Montgomery Multiplication
18	Abdulah Abdulah Zadeh	High Speed Modular Divider Based on GCD Algorithm.	ICICS	2007	DBLP DOI BibTeX RDF	GCD algorithm, Radix four, Finite Field, ECC
18	Chih-Peng Fan, Guo-An Su	A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Marcelo E. Kaihara, Naofumi Takagi	A Hardware Algorithm for Modular Multiplication/Division.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	modular division, cryptography, Computer arithmetic, modular multiplication, redundant representation, hardware algorithm
18	Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano	A Novel Unified Architecture for Public-Key Cryptography.	DATE	2005	DBLP DOI BibTeX RDF
18	Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu	Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	James A. Muir, Douglas R. Stinson	New Minimal Weight Representations for Left-to-Right Window Methods.	CT-RSA	2005	DBLP DOI BibTeX RDF
18	Kyle Kelley, David Money Harris	Very High Radix Scalable Montgomery Multipliers.	IWSOC	2005	DBLP DOI BibTeX RDF
18	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
18	Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama	FPGA Implementation of Fast Radix 4 Division Algorithm.	IWSOC	2004	DBLP DOI BibTeX RDF	fast division, radix 4 division, quotient selection, Field programmable gate arrays (FPGAs)
18	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	Efficient pruning algorithms for the DFT computation for a subset of output samples.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
18	Shing-Chow Chan, Kai Man Tsui	Multiplier-less real-valued FFT-like transformation (ML-RFFT) and related real-valued transformations.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
18	S. C. Chan 0001, P. M. Yiu	A multiplier-less 1-D and 2-D fast Fourier transform-like transformation using sum-of-powers-of-two (SOPOT) coefficients.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu	Design of an efficient FFT processor for DAB system.	ISCAS (4)	2001	DBLP DOI BibTeX RDF