Search results for "Rambus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
138	Richard H. Stern	Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties.	IEEE Micro	2007	DBLP DOI BibTeX RDF	Rambus, antitrust violation, skullduggery, Secret Squirrel, DDR SDRAM, JEDEC, standardization, law, patents, SDRAM
110	Richard H. Stern	FTC Piles onto Rambus' Standardization Skullduggery.	IEEE Micro	2002	DBLP DOI BibTeX RDF
96	Richard H. Stern	Another Update on Standardization Skullduggery.	IEEE Micro	2001	DBLP DOI BibTeX RDF
96	Richard H. Stern	More standardization skullduggery.	IEEE Micro	2001	DBLP DOI BibTeX RDF
91	Richard H. Stern	Weird Turn of Events in Continuing Rambus Saga.	IEEE Micro	2003	DBLP DOI BibTeX RDF
86	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Designing a Modern Memory Hierarchy with Hardware Prefetching.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
71	Philip Machanick, Pierre Salverda, Lance Pompe	Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy.	ASPLOS	1998	DBLP DOI BibTeX RDF
67	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
67	J. Bruce Millar, Peter Gillingham	Two High-Bandwidth Memory Bus Structures.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF	SLDRAM, Direct Rambus, DRAM, memory design
67	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
58	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.	HPCA	2001	DBLP DOI BibTeX RDF
52	Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf	Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.	HPCA	1999	DBLP DOI BibTeX RDF
38	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	A Performance Comparison of Contemporary DRAM Architectures.	ISCA	1999	DBLP DOI BibTeX RDF
33	Ibtissem Seghaier, Sofiène Tahar	Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects.	NEWCAS	2018	DBLP DOI BibTeX RDF
33	Richard H. Stern	One of the Last Updates on Rambus Standardization Skullduggery.	IEEE Micro	2009	DBLP DOI BibTeX RDF
33	Richard H. Stern	Micro Law: An End to the Rambus Skullduggery Saga.	IEEE Micro	2009	DBLP DOI BibTeX RDF
33	John Privitera, Steven Woo, Craig Soldat	Pattern generation tools for the development of memory core test patterns for Rambus devices.	ITC	2000	DBLP DOI BibTeX RDF
33	Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina	A 2000-MOPS embedded RISC processor with a Rambus DRAM controller.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
33	Richard Crisp	Direct RAMbus technology: the new main memory standard.	IEEE Micro	1997	DBLP DOI BibTeX RDF
33	K. D. Jones, J. P. Privitera	The Automatic Generation of Functional Test Vectors for Rambus Designs.	DAC	1996	DBLP DOI BibTeX RDF
19	Mark R. Greenstreet, Suwen Yang	Verifying start-up conditions for a ring oscillator.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	formal verification, dynamical systems, oscillators
19	Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem	Near-Memory Caching for Improved Energy Consumption.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Memory power management, Cached DRAM, Power Management, Energy-aware systems, Memory design
19	P. Yeung, A. Torres, P. Batra	Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor.	DATE	2007	DBLP DOI BibTeX RDF
19	Anand Eswaran, Raj Rajkumar	Energy-Aware Memory Firewalling for QoS-Sensitive Applications.	ECRTS	2005	DBLP DOI BibTeX RDF
19	Zhichun Zhu, Zhao Zhang 0010	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.	HPCA	2005	DBLP DOI BibTeX RDF
19	Zhichun Zhu, Zhao Zhang 0010, Xiaodong Zhang 0001	Fine-Grain Priority Scheduling on Multi-Channel Memory Systems.	HPCA	2002	DBLP DOI BibTeX RDF	DRAM configurations, fine-grain priority scheduling, memory-intensive applications and multi-channel memory systems
19	Vinodh Cuppu, Bruce L. Jacob	Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
19	Sally A. McKee, William A. Wulf, James H. Aylor, Robert H. Klenke, Maximo H. Salinas, Sung I. Hong, Dee A. B. Weikle	Dynamic Access Ordering for Streamed Computations.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Memory systems architecture, memory access ordering, memory access scheduling, memory bandwidth, memory latency
19	Chengqiang Zhang, Sally A. McKee	Hardware-only stream prefetching and dynamic access ordering.	ICS	2000	DBLP DOI BibTeX RDF
19	Norman Margolus	An FPGA architecture for DRAM-based systolic computations.	FCCM	1997	DBLP DOI BibTeX RDF