|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 4 occurrences of 4 keywords
|
|
|
|
|
Results
Found 4 publication records. Showing 4 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 70 | W. Lynn Gallagher, Chuan-lin Wu |
Evaluation of a memory hierarchy for the MTS multithreaded processor.  |
ICPADS  |
1997 |
DBLP DOI BibTeX RDF |
memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache |
| 24 | Mandar A. Mathuré, Vinay Jonnalagadda, Janusz Zalewski |
Heterogeneous Architecture and Testbed for Simulation of Large-Scale Real-Time Systems. |
DS-RT |
2003 |
DBLP DOI BibTeX RDF |
|
| 24 | Janusz Zalewski |
Automatic Development Tools in Software Engineering Courses. |
CSEE&T |
2000 |
DBLP DOI BibTeX RDF |
|
| 24 | Christoph Schaffer, R. J. Raschhofer, A. Simma |
EaSy-Sim: A Tool Environment for the Design of Complex, Real-Time Systems. |
EUROCAST |
1995 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #4 of 4 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")
data released under the ODC-BY 1.0 license