The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for phrase SOC-test (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1998-2002 (36) 2003 (37) 2004 (21) 2005-2006 (28) 2007 (19) 2008 (17) 2009-2011 (15) 2012-2015 (22) 2016 (17) 2017 (17) 2018 (20) 2019 (16) 2021 (1)
Publication types (Num. hits)
article(56) inproceedings(205) proceedings(5)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 104 occurrences of 46 keywords

Results
Found 266 publication records. Showing 266 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
84Sandeep Kumar Goel, Erik Jan Marinissen SOC test architecture design for efficient utilization of test bandwidth. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization
82Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu STEAC: A Platform for Automatic SOC Test Integration. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
65Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee An SOC Test Integration Platform and Its Industrial Realization. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty Power-aware SoC test planning for effective utilization of port-scalable testers. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF port-scalable testers, test access architecture, integer linear programming, SoC test
57Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy On Concurrent Test of Core-Based SOC Design. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF concurrent SOC test, pin mapping, 2-dimensional bin-packing, test scheduling
55Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty SOC test planning using virtual test access architectures. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Sandeep Koranne, Vikram Iyengar On the Use of k-tuples for SoC Test Schedule Representation. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
53Qiang Xu 0001, Nicola Nicolici Modular SOC testing with reduced wrapper count. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
51Erik Larsson, Zebo Peng An Integrated Framework for the Design and Optimization of SOC Test Solutions. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning
50Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka A SoC Test Strategy Based on a Non-Scan DFT Method. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF non-scan DFT, high level design and test, SoC test
50Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Sandeep Kumar Goel, Erik Jan Marinissen Effective and Efficient Test Architecture Design for SOCs. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Sandeep Koranne Formulating SoC test scheduling as a network transportation problem. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
44Anuja Sehgal, Krishnendu Chakrabarty Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
44Anuja Sehgal, Krishnendu Chakrabarty Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
44Praveen Bhojwani, Rabi N. Mahapatra An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
41Quming Zhou, Kedarnath J. Balakrishnan Test cost reduction for SoC using a combined approach to test data compression and test scheduling. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. Search on Bibsonomy ICCTA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang SoC test scheduling using the B-tree based floorplanning technique. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Sandeep Koranne Design of reconfigurable access wrappers for embedded core based SoC test. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Srivaths Ravi 0001, Niraj K. Jha Synthesis of System-on-a-chip for Testability. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
40Ozgur Sinanoglu, Alex Orailoglu Test power reductions through computationally efficient, decoupled scan chain modifications. Search on Bibsonomy IEEE Trans. Reliab. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Sandeep Kumar Goel, Erik Jan Marinissen Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
38Dan Zhao 0001, Yi Wang 0007 MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Jin-Ho Ahn, Sungho Kang SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing. Search on Bibsonomy ICIC (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Sandeep Koranne Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Ozgur Sinanoglu, Alex Orailoglu Partial Core Encryption for Performance-Efficient Test of SOCs. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Sudarshan Bahukudumbi, Krishnendu Chakrabarty Wafer-Level Modular Testing of Core-Based SoCs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Sandeep Kumar Goel, Erik Jan Marinissen A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF TAM and wrapper design, test scheduling, SOC-test
35Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
35Praveen Bhojwani, Rabi N. Mahapatra Robust Concurrent Online Testing of Network-on-Chip-Based SoCs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Core-based systems, test wrapper, system-on-a-chip, test scheduling, test access mechanism, testing time, rectangle packing
34Sandeep Koranne On Test Scheduling for Core-Based SOCs. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara TAM Design and Optimization for Transparency-Based SoC Test. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF TAM design, transparency, ILP, SoC test
32Érika F. Cota, Luigi Carro, Marcelo Lubaszewski Reusing an on-chip network for the test of core-based systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test
32Ozgur Sinanoglu Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
32Ozgur Sinanoglu, Alex Orailoglu Scan Power Minimization through Stimulus and Response Transformations. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Cheng-Wen Wu SOC Testing Methodology and Practice. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
31Ozgur Sinanoglu, Alex Orailoglu Autonomous Yet Deterministic Test of SOC Cores. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
31Vikram Iyengar, Krishnendu Chakrabarty System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Yu Huang 0005, Sudhakar M. Reddy, Wu-Tung Cheng Core - Clustering Based SOC Test Scheduling Optimization. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Sandeep Kumar Goel, Erik Jan Marinissen On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
29Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Vikram Iyengar, Krishnendu Chakrabarty Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. Search on Bibsonomy VTS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
26Lin Huang 0002, Feng Yuan, Qiang Xu 0001 On reliable modular testing with vulnerable test access mechanisms. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF modular testing, test access mechanisms, reliable test
26Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen Scheduling-based test-case generation for verification of multimedia SoCs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test generation, system on a chip, functional verification
26James Chin, Mehrdad Nourani SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian A Hierarchical Infrastructure for SoC Test Management. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang 0005 SOC Test Scheduling Using Simulated Annealing. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Hari Vijay Venkatanarayanan, Michael L. Bushnell An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan Re-configurable embedded core test protocol. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Ozgur Sinanoglu, Tsvetomir Petrov A non-intrusive isolation approach for soft cores. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001 Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25K. Nikila, Rubin A. Parekhji DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
24Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski Test planning for modular testing of hierarchical SOCs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
24Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Efficient test access mechanism optimization for system-on-chip. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici Test Data Compression: The System Integrator's Perspective. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
24Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Efficient Wrapper/TAM Co-Optimization for Large SOCs. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
23Sudarshan Bahukudumbi, Krishnendu Chakrabarty Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
23Sudarshan Bahukudumbi, Krishnendu Chakrabarty Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
23Qiang Xu 0001, Nicola Nicolici Multifrequency TAM design for hierarchical SOCs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
23Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
22Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF test wrapper, integer linear programming, test access mechanism (TAM), testing time, Embedded core testing
21Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Search on Bibsonomy Asian Test Symposium The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
21Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
21Martin Schrader, Roderick McConnell SoC Design and Test Considerations. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
21Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs. Search on Bibsonomy VTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Ying Zhang 0040, Li Ling, Jianhui Jiang, Jie Xiao 0003 Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition. Search on Bibsonomy J. Electron. Test. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
20Chunlei Mei, Maoxiang Yi, Zhifei Shen Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination. Search on Bibsonomy TrustCom The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
20Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
20Hong-Sik Kim, Sungho Kang 0001, Michael S. Hsiao A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Keyword System on a chip, Test compression, Low power testing, Scan testing
20Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Thermal-aware testing, Test scheduling, SoC testing
20Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang Process Algebra Based SoC Test Scheduling for Test Time Minimization. Search on Bibsonomy ISVLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
20Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You Test Efficiency Analysis and Improvement of SOC Test Platforms. Search on Bibsonomy ATS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Zhiyuan He 0002, Zebo Peng, Petru Eles Power constrained and defect-probability driven SoC test scheduling with test set partitioning. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling. Search on Bibsonomy ITC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng SOC Test Scheduling with Test Set Sharing and Broadcasting. Search on Bibsonomy Asian Test Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
20Chakunta Venkata Guru Rao, Dipanwita Roy Chowdhury A new design-for-test technique for reducing SOC test time. Search on Bibsonomy ASP-DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Vikram Iyengar, Anshuman Chandra A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Sudhakar M. Reddy Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
20Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi A Selective Trigger Scan Architecture for VLSI Testing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
20Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie 0001 Test-access mechanism optimization for core-based three-dimensional SOCs. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
20Rani S. Ghaida, Payman Zarkesh-Ha Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. Search on Bibsonomy DFT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
20Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
20Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Search on Bibsonomy Asian Test Symposium The full citation details ... 2003 DBLP  DOI  BibTeX  RDF wrapper, design for test, test scheduling, test access mechanism
20Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
19Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee Test pattern generation and clock disabling for simultaneous test time and power reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
19Sandeep Koranne A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF embedded core based test scheduling, reconfigurable wrapper, parallel scheduling of malleable tasks, system-on-chip test, VLSI test
18Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra Response compaction for system-on-a-chip based on advanced convolutional codes. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF X bits masking, aliasing, convolutional code, SOC test, response compaction
18Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes Reducing test time with processor reuse in network-on-chip based systems. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
18Krishna Sekar, Sujit Dey LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF LI-BIST, crosstalk test, BIST, SoC test, low-power test
Displaying result #1 - #100 of 266 (100 per page; Change: )
Pages: [1][2][3][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license