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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 94 occurrences of 68 keywords
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Results
Found 80 publication records. Showing 80 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
135 | Jakob Engblom |
Why SpecInt95 Should Not Be Used to Benchmark Embedded Systems Tools. |
Workshop on Languages, Compilers, and Tools for Embedded Systems |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Nitzan Weinberg, David Nagle |
Dynamic Elimination of Pointer-Expressions. |
IEEE PACT |
1998 |
DBLP DOI BibTeX RDF |
pointer-expression, sphinx, sub-expression, SPECint95, memory address, performance analysis, compiler, locality, speech recognition, dynamic, microprocessor, mpeg, cache memory, microarchitecture, jpeg, value, spatial, memory bandwidth, data reuse, temporal, pointer, conditional execution |
44 | David M. Brooks, Margaret Martonosi |
Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. |
ACM Trans. Comput. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
44 | David M. Brooks, Margaret Martonosi |
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. |
HPCA |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Sohum Sohoni, Rui Min, Zhiyong Xu, Yiming Hu |
A study of memory system performance of multimedia applications. |
SIGMETRICS/Performance |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Soner Önder, Rajiv Gupta 0001 |
Load and store reuse using register file contents. |
ICS |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Amarildo T. da Costa, Felipe M. G. França, Eliseu M. Chaves Filho |
The Dynamic Trace Memorization Reuse Technique. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Quinn Jacobson, James E. Smith 0001 |
Trace preconstruction. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Seongmoo Heo, Ronny Krashinsky, Krste Asanovic |
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Josep M. Codina, F. Jesús Sánchez, Antonio González 0001 |
Virtual Cluster Scheduling Through the Scheduling Graph. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Youfeng Wu, Yong-Fong Lee |
Hardware-Software Collaborative Techniques for Runtime Profiling and Phase Transition Detection. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
runtime profiling, phase transition detection, hardware-software collaboration, dynamic optimizations |
15 | Xin Lu, Yuzhuo Fu |
Reducing leakage power in instruction cache using WDC for embedded processors. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff |
Generating new general compiler optimization settings. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
compiler tuning, compiler optimization, iterative compilation |
15 | Veerle Desmet, Lieven Eeckhout, Koen De Bosschere |
Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Masayo Haneda, Peter M. W. Knijnenburg, Harry A. G. Wijshoff |
Optimizing general purpose compiler optimization. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
back-end optimization, compiler switches, compiler tuning, statistical analysis |
15 | Daniel Ortega, Mateo Valero, Eduard Ayguadé |
Dynamic Memory Instruction Bypassing. |
Int. J. Parallel Program. |
2004 |
DBLP DOI BibTeX RDF |
memory bypassing, Prefetching |
15 | Ramon Canal, Antonio González 0001, James E. Smith 0001 |
Software-Controlled Operand-Gating. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Youfeng Wu, Yong-Fong Lee |
Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling. |
Asia-Pacific Computer Systems Architecture Conference |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Deniz Balkan, John Kalamatianos, David R. Kaeli |
A Study of Errant Pipeline Flushes Caused by Value Misspeculation. |
SBAC-PAD |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy |
An evaluation of speculative instruction execution on simultaneous multithreaded processors. |
ACM Trans. Comput. Syst. |
2003 |
DBLP DOI BibTeX RDF |
multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading |
15 | Chao-ying Fu, Jill T. Bodine, Thomas M. Conte |
Modeling Value Speculation: An Optimal Edge Selection Problem. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
optimal edge selection, critical path reduction, Value prediction, data dependence graph, value speculation |
15 | Mahesh Mamidipaka, Nikil D. Dutt |
On-chip Stack Based Memory Organization for Low Power Embedded Architectures. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Ortega, Eduard Ayguadé, Mateo Valero |
Dynamic memory instruction bypassing. |
ICS |
2003 |
DBLP DOI BibTeX RDF |
on-chip memory management, superscalar processors |
15 | Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau |
Reducing data cache energy consumption via cached load/store queue. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
LSQ, load queue, store queue, low power, cache, memory, low energy, low latency |
15 | Li-Ling Chen, Youfeng Wu |
Aggressive Compiler Optimization and Parallelization with Thread-Level Speculation. |
ICPP |
2003 |
DBLP DOI BibTeX RDF |
high-performance architecture and region formation, compiler optimizations, speculative execution, thread-level parallelism |
15 | Martin Burtscher, Benjamin G. Zorn |
Hybrid Load-Value Predictors. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
load-value predictor, performance metrics, Value prediction, value locality, hybrid predictor |
15 | Mary D. Brown, Yale N. Patt |
Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. |
HPCA |
2002 |
DBLP DOI BibTeX RDF |
redundant binary, limited bypass, pipelined register file, signed digit |
15 | Huiyang Zhou, Thomas M. Conte |
Code Size Efficiency in Global Scheduling for ILP Processors. |
Interaction between Compilers and Computer Architectures |
2002 |
DBLP DOI BibTeX RDF |
Code Size Efficiency, I-cache Performance, Code Replication, Tail Duplication, Optimal Code Size Efficiency, Diminishing Returns, Quantitative Measure, Instruction Level Parallelism (ILP) |
15 | George C. Necula, Scott McPeak, Westley Weimer |
CCured: type-safe retrofitting of legacy code. |
POPL |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Mark Probst, Andreas Krall, Bernhard Scholz |
Register Liveness Analysis for Optimizing Dynamic Binary Translation. |
WCRE |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Augustus K. Uht, Alireza Khalafi, David Morano, Marcos de Alba, David R. Kaeli |
Realizing High IPC Using Time-Tagged Resource-Flow Computing. |
Euro-Par |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001 |
Dual path instruction processing. |
ICS |
2002 |
DBLP DOI BibTeX RDF |
branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation |
15 | Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz |
Difficult-Path Branch Prediction Using Subordinate Microthreads. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
high performance microprocessor, SSMT, microthread, branch prediction, microarchitecture, SMT, helper thread |
15 | Lucian Codrescu, D. Scott Wills, James D. Meindl |
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
Thread speculation, multiscalar, parallelization, chip-multiprocessor, multithreading, value prediction |
15 | Waleed Meleis, Alexandre E. Eichenberger, Ivan D. Baev |
Scheduling Superblocks with Bound-Based Branch Trade-Offs. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
ILP compiler technique, lower bound, scheduling heuristic, Superblock |
15 | Chen-Yong Cher, T. N. Vijaykumar |
Skipper: a microarchitecture for exploiting control-flow independence. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Eduard Mehofer, Bernhard Scholz |
A Novel Probabilistic Data Flow Framework. |
CC |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka |
Improving Conditional Branch Prediction on Speculative Multithreading Architectures. |
Euro-Par |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons |
Register-sensitive selection, duplication, and sequencing of instructions. |
ICS |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Seongmoo Heo, Ronny Krashinsky, Krste Asanovic |
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Youfeng Wu, Dong-yuan Chen, Jesse Fang |
Better exploration of region-level value locality with integrated computation reuse and value prediction. |
ISCA |
2001 |
DBLP DOI BibTeX RDF |
Systems Application Architecture |
15 | Sang Jeong Lee, Pen-Chung Yew |
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Sang Jeong Lee, Yuan Wang, Pen-Chung Yew |
Decoupled Value Prediction on Trace Processors. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
Wide-issue superscalar processors, Trace processors, Speculative execution, Value prediction |
15 | Ramon Canal, Joan-Manuel Parcerisa, Antonio González 0001 |
Dynamic Cluster Assignment Mechanisms. |
HPCA |
2000 |
DBLP DOI BibTeX RDF |
dynamic code partitioning, steering logic, Clustered microarchitectures, dynamically scheduled processors |
15 | Mihai Budiu, Majd F. Sakr, Kip Walker, Seth Copen Goldstein |
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations. |
Euro-Par |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia |
Dynamo: a transparent dynamic optimization system. |
PLDI |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Martin Burtscher, Benjamin G. Zorn |
Hybridizing and Coalescing Load Value Predictors. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Jun Yang 0002, Rajiv Gupta 0001 |
Load Redundancy Removal through Instruction Reuse. |
ICPP |
2000 |
DBLP DOI BibTeX RDF |
|
15 | José-Lorenzo Cruz, Antonio González 0001, Mateo Valero, Nigel P. Topham |
Multiple-banked register file architectures. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
bypass logic, register file architecture, register file cache, dynamically-scheduled processor |
15 | Ryan N. Rakvic, Bryan Black, John Paul Shen |
Completion time multiple branch prediction for enhancing trace cache performance. |
ISCA |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark |
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
instruction window size, register-update unit, simulation, cache, sampling, branch prediction, Microarchitecture, trade-offs, out-of-order execution |
15 | Martin Burtscher, Benjamin G. Zorn |
Exploring Last n Value Prediction. |
IEEE PACT |
1999 |
DBLP DOI BibTeX RDF |
predictor design, value prediction, processor performance, value locality, behavior prediction |
15 | Lucian Codrescu, D. Scott Wills |
On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm. |
IEEE PACT |
1999 |
DBLP DOI BibTeX RDF |
Thread Partitioning, Multiscalar, Thread Speculation, Speculative Multithreading, Dynamic Partitioning |
15 | Alexandre E. Eichenberger, Waleed Meleis |
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
ILP compiler technique, weighted completion time, lower bound, scheduling heuristic, Superblock |
15 | Mayan Moudgill, Pradip Bose, Jaime H. Moreno |
Validation of Turandot, a fast processor model for microarchitecture exploration. |
IPCCC |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Jonathan Combs, Candice Bechem Combs, John Paul Shen |
Mispredicted Path Cache Effects. |
Euro-Par |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind |
Execution-Based Scheduling for VLIW Architectures. |
Euro-Par |
1999 |
DBLP DOI BibTeX RDF |
INSTRUCTION-LEVEL PARALLELISM, SUPERSCALAR, BINARY TRANSLATION, DYNAMIC COMPILATION |
15 | Alberto Ferreira de Souza, Peter Rounce |
Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions. |
IPPS/SPDP |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata |
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Lucian Codrescu, D. Scott Wills |
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Ben-Chung Cheng, Wen-mei W. Hwu |
An Empirical Study of Function Pointers Using SPEC Benchmarks. |
LCPC |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt |
Simultaneous Subordinate Microthreading (SSMT). |
ISCA |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Bryan Black, Bohuslav Rychlik, John Paul Shen |
The Block-Based Trace Cache. |
ISCA |
1999 |
DBLP DOI BibTeX RDF |
|
15 | A. V. S. Sastry, Roy Dz-Ching Ju |
A New Algorithm for Scalar Register Promotion based on SSA Form. |
PLDI |
1998 |
DBLP DOI BibTeX RDF |
|
15 | S. Subramanya Sastry, Subbarao Palacharla, James E. Smith 0001 |
Exploiting Idle Floating-Point Resources for Integer Execution. |
PLDI |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Fred C. Chow, Robert Kennedy, Shin-Ming Liu, Raymond Lo, Peng Tu |
Register Promotion by Partial Redundancy Elimination of Loads and Stores. |
PLDI |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Mark R. Swanson, Leigh Stoller, John B. Carter |
Increasing TLB Reach Using Superpages Backed by Shadow Memory. |
ISCA |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Eitan Federovsky, Meir Feder, Shlomo Weiss |
Branch Prediction Based on Universal Data Compression Algorithms. |
ISCA |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Artur Klauser, Abhijit Paithankar, Dirk Grunwald |
Selective Eager Execution on the PolyPath Architecture. |
ISCA |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Toni Juan, Sanji Sanjeevan, Juan J. Navarro |
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction. |
ISCA |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Jared Stark, Marius Evers, Yale N. Patt |
Variable Length Path Branch Prediction. |
ASPLOS |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte |
Value Speculation Scheduling for High Performance Processors. |
ASPLOS |
1998 |
DBLP DOI BibTeX RDF |
VLIW instruction schedulings, instruction level parallelism, value prediction, value speculation |
15 | Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith 0001 |
Trace Processors. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
trace processors, multiscalar processors, next trace prediction, selective reissuing, context-based value prediction, trace cache |
15 | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt |
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
high bandwidth fetch mechanisms, wide issue machines, inactive issue, speculative execution, trace cache, partial matching |
15 | Jonathan Babb, Matthew I. Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael B. Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal |
The RAW benchmark suite: computation structures for general purpose computing. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
|
15 | Andrew Ayers, Robert Gottlieb, Richard Schooler |
Aggressive Inlining. |
PLDI |
1997 |
DBLP DOI BibTeX RDF |
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15 | Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt |
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
two-level branch prediction, branch prediction, speculative execution, superscalar |
15 | Ravi Nair, Martin E. Hopkins |
Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
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15 | Po-Yung Chang, Eric Hao, Yale N. Patt |
Target Prediction for Indirect Jumps. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
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15 | Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt |
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. |
MICRO |
1996 |
DBLP DOI BibTeX RDF |
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