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Searching for STARI with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1995 (2) 1997 (1) 1999 (2) 2003 (1) 2004 (1)
Publication types (Num. hits)
inproceedings(7)
Venues (Conferences, Journals, ...)
ASYNC(2) ATVA(1) CAV(1) CHARME(1) ICCD(1) ISMVL(1)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 13 occurrences of 12 keywords

Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
171Mark R. Greenstreet Implementing a STARI chip. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits
72Ajanta Chakraborty, Mark R. Greenstreet Efficient Self-Timed Interfaces for Crossing Clock Domains. Search on Bibsonomy ASYNC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
72Marius Bozga, Oded Maler, Stavros Tripakis Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics. Search on Bibsonomy CHARME The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
66Serdar Tasiran, Robert K. Brayton STARI: A Case Study in Compositional and Hierarchical Timing Verification. Search on Bibsonomy CAV The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
57Jens Kargaard Madsen, Stephen I. Long A High-Speed Interconnect Network Using Ternary Logic. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication
24Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. Search on Bibsonomy ATVA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24Tomohiro Yoneda, Hiroshi Ryu Timed Trace Theoretic Verification Using Partial Order Reduction. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
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