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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 13 occurrences of 12 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
171 | Mark R. Greenstreet |
Implementing a STARI chip. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits |
72 | Ajanta Chakraborty, Mark R. Greenstreet |
Efficient Self-Timed Interfaces for Crossing Clock Domains. |
ASYNC |
2003 |
DBLP DOI BibTeX RDF |
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72 | Marius Bozga, Oded Maler, Stavros Tripakis |
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics. |
CHARME |
1999 |
DBLP DOI BibTeX RDF |
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66 | Serdar Tasiran, Robert K. Brayton |
STARI: A Case Study in Compositional and Hierarchical Timing Verification. |
CAV |
1997 |
DBLP DOI BibTeX RDF |
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57 | Jens Kargaard Madsen, Stephen I. Long |
A High-Speed Interconnect Network Using Ternary Logic. |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication |
24 | Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers |
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. |
ATVA |
2004 |
DBLP DOI BibTeX RDF |
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24 | Tomohiro Yoneda, Hiroshi Ryu |
Timed Trace Theoretic Verification Using Partial Order Reduction. |
ASYNC |
1999 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #7 of 7 (100 per page; Change: )
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