Search results for "SUPERSCALAR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
86	Marc Tremblay, Bill Joy 0001, Ken Shin	A three dimensional register file for superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
78	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
76	Enric Tejedor, Rosa M. Badia	COMP Superscalar: Bringing GRID Superscalar and GCM Together.	CCGRID	2008	DBLP DOI BibTeX RDF	Grid Component Model, Grid-unaware applications, concurrency exploitation, performance optimization, Component-based software engineering
72	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
63	Josep Lluís Larriba-Pey, Daniel Jiménez-González, Juan J. Navarro	An Analysis of Superscalar Sorting Algorithms on an R8000 Processor.	SCCC	1997	DBLP DOI BibTeX RDF	superscalar sorting algorithms, R8000 processor, in-memory sorting algorithms, Quick sort, Heap sort, Multiway merge, parallel algorithms, locality, superscalar architectures, Radix sort, Bucket sort
63	Larry Carter, Jeanne Ferrante, Susan Flynn Hummel	Hierarchical tiling for improved superscalar performance.	IPPS	1995	DBLP DOI BibTeX RDF	hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage
59	Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero	A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications.	Theory Comput. Syst.	2003	DBLP DOI BibTeX RDF
59	Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero	A cost effective architecture for vectorizable numerical and multimedia applications.	SPAA	2001	DBLP DOI BibTeX RDF
59	Vimal K. Reddy, Eric Rotenberg	Coverage of a microarchitecture-level fault check regimen in a superscalar processor.	DSN	2008	DBLP DOI BibTeX RDF
59	Rosa M. Badia, Jesús Labarta, Raül Sirvent, Josep M. Pérez, José M. Cela, Rogeli Grima	Programming Grid Applications with GRID Superscalar.	J. Grid Comput.	2003	DBLP DOI BibTeX RDF	Grid programming models, Grid middleware
59	André Seznec, Eric Toullec, Olivier Rochecouste	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.	MICRO	2002	DBLP DOI BibTeX RDF
57	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Superscalar Coprocessor for High-Speed Curve-Based Cryptography.	CHES	2006	DBLP DOI BibTeX RDF	curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
57	Graham P. Jones, Nigel P. Topham	A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine.	MICRO	1997	DBLP DOI BibTeX RDF	Access Decoupling, Superscalar, out of order execution, latency hiding
57	Avi Mendelson, Neeraj Suri	Designing High-Performance & Reliable Superscalar Architectures: The out of Order Reliable Superscalar (O3RS) Approach.	DSN	2000	DBLP DOI BibTeX RDF	Transient Errors/Recovery, Pipelines, Superscalar architectures
55	Bo Kågström	Management of Deep Memory Hierarchies - Recursive Blocked Algorithms and Hybrid Data Structures for Dense Matrix Computations.	PARA	2004	DBLP DOI BibTeX RDF	automatic variable blocking, hybrid data structures, superscalar kernels, SMP parallelization, library software, ESSL, RECSY, periodic systems, factorizations, recursion, superscalar, LAPACK, level 3 BLAS, dense linear algebra, GEMM-based, SLICOT, matrix equations
55	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design.	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
55	Roger Collins, Gordon B. Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
55	Steven Wallace, Nirav Dagli, Nader Bagherzadeh	Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
51	Rafael R. dos Santos, Philippe Olivier Alexandre Navaux	Analysing a Multistreamed Superscalar Speculative Fetch Mechanism.	Euro-Par	1998	DBLP DOI BibTeX RDF
51	Anthony C. J. Fox, Neal A. Harman	Algebraic Models of Superscalar Microprocessor Implementations: A Case Study.	Prospects for Hardware Foundations	1998	DBLP DOI BibTeX RDF
51	Soohong P. Kim, Raymond Hoare, Henry G. Dietz	VLIW Across Multiple Superscalar Processors on a Single Chip.	IEEE PACT	1997	DBLP DOI BibTeX RDF
49	Krishna M. Kavi, Roberto Giorgi, Joseph Arul	Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	superscalar, Thread Level Parallelism, Multithreaded architectures, decoupled architectures, dataflow architectures
48	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
48	Patrick Ndai, Swarup Bhunia, Amit Agarwal 0001, Kaushik Roy 0001	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
48	Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani	Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning.	DSN	2007	DBLP DOI BibTeX RDF	overclocking, Reliability, Fault-Tolerant Computing, Dynamic, Superscalar processor
48	Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose	Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling
48	Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Power efficient comparators for long arguments in superscalar processors.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power comparators, superscalar datapath
48	Kanad Ghose	Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	instruction dispatching, instruction issue, window buffer, superscalar processor, power minimization
48	Chris Stolte, Robert P. Bosch Jr., Pat Hanrahan, Mendel Rosenblum	Visualizing Application Behavior on Superscalar Processors.	INFOVIS	1999	DBLP DOI BibTeX RDF	Computer systems visualization, superscalar processors, visualization systems
48	Bernard Goossens, Duc Thang Vu	Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.	ISPAN	1996	DBLP DOI BibTeX RDF	Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
46	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
42	Yinong Zhang, George B. Adams III	Performance Modeling and Code Partitioning for the DS Architecture.	ISCA	1998	DBLP DOI BibTeX RDF
42	Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya	Performance Comparison of ILP Machines with Cycle Time Evaluation.	ISCA	1996	DBLP DOI BibTeX RDF
42	Kiyeon Lee, Shayne Evans, Sangyeun Cho	Accurately approximating superscalar processor performance from traces.	ISPASS	2009	DBLP DOI BibTeX RDF
42	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
42	Mojtaba Shakeri, Abolfazl Toroghi Haghighat, Mohammad K. Akbari	Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors.	ITNG	2007	DBLP DOI BibTeX RDF
42	Josep M. Pérez, Rosa M. Badia, Jesús Labarta	Including SMP in Grids as Execution Platform and Other Extensions in GRID Superscalar.	e-Science	2006	DBLP DOI BibTeX RDF
42	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
42	Vasilis Dialinos, Rosa M. Badia, Raül Sirvent, Josep M. Pérez, Jesús Labarta	Implementing phylogenetic inference with GRID superscalar.	CCGRID	2005	DBLP DOI BibTeX RDF
42	Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi	Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures.	MICRO	2004	DBLP DOI BibTeX RDF
42	Tejas Karkhanis, James E. Smith 0001	A First-Order Superscalar Processor Model.	ISCA	2004	DBLP DOI BibTeX RDF
42	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors.	ISCA	2003	DBLP DOI BibTeX RDF
42	Tony Werner, Venkatesh Akella	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism.	ASYNC	2001	DBLP DOI BibTeX RDF
42	Victor V. Zyuban, Peter M. Kogge	Optimization of high-performance superscalar architectures for energy efficiency.	ISLPED	2000	DBLP DOI BibTeX RDF
42	Simonjit Dutta, Manoj Franklin	Control Flow Prediction Schemes for Wide-Issue Superscalar Processors.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP)
42	Esther Stümpel, Michael Thies, Uwe Kastens	VLIW Compilation Techniques for Superscalar Architectures.	CC	1998	DBLP DOI BibTeX RDF
42	Andreas Unger, Eberhard Zehendner	Tuning the GNU Instruction Scheduler to Superscalar Microprocessors.	EUROMICRO	1997	DBLP DOI BibTeX RDF
42	Manu Gulati, Nader Bagherzadeh	Performance Study of a Multithreaded Superscalar Microprocessor.	HPCA	1996	DBLP DOI BibTeX RDF	multithreading, instruction-level parallelism, Superscalars, out-of-order execution
42	Hong Chich Chou, Chung-Ping Chung	An Optimal Instruction Scheduler for Superscalar Processor.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
42	Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv	VLIW Compilation Techniques in a Superscalar Environment.	PLDI	1994	DBLP DOI BibTeX RDF	profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000
42	Michael D. Smith 0001, Mark Horowitz, Monica S. Lam	Efficient Superscalar Performance Through Boosting.	ASPLOS	1992	DBLP DOI BibTeX RDF
40	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
40	Jessica H. Tseng, Krste Asanovic	A Speculative Control Scheme for an Energy-Efficient Banked Register Fil.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	speculative control, Low-power, superscalar, register file, simultaneous multithreading
40	William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang	Tolerating data access latency with register preloading.	ICS	1992	DBLP DOI BibTeX RDF	VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis
40	Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras	Interval-based models for run-time DVFS orchestration in superscalar processors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
40	Rosa M. Badia, D. Du, Eduardo Huedo, Antonis C. Kokossis, Ignacio Martín Llorente, Rubén S. Montero, Marc de Palol, Raül Sirvent, Constantino Vázquez	Integration of GRID Superscalar and GridWay Metascheduler with the DRMAA OGF Standard.	Euro-Par	2008	DBLP DOI BibTeX RDF	DRMAA, GRID superscalar, GridWay Metascheduler, Grid Computing
40	William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame	Modeling Assembly Instruction Timing in Superscalar Architectures.	ISSS	2002	DBLP DOI BibTeX RDF	assembly-level analysis, performance estimation, superscalar architectures
40	Jorge E. Carrillo, Paul Chow	The effect of reconfigurable units in superscalar processors.	FPGA	2001	DBLP DOI BibTeX RDF	OneChip, superscalar processors, reconfigurable processors
40	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
40	Santiago Rodríguez de la Fuente, M. Isabel García Clemente, Rafael Méndez Cavanillas	Teaching computer architecture with a new superscalar processor emulator.	ITiCSE	1999	DBLP DOI BibTeX RDF	education, pipeline, emulation, cache memory, superscalar
40	Srivatsan Srinivasan, Lizy Kurian John	On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors.	ICCD	1999	DBLP DOI BibTeX RDF	hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer
40	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
40	Frank P. Burns, Albert Koelmans, Alexandre Yakovlev	Analysing Superscalar Processor Architectures with Coloured Petri Nets.	Int. J. Softw. Tools Technol. Transf.	1998	DBLP DOI BibTeX RDF	Asynchronous processors, Modelling, Real-time systems, Worst case execution time, Coloured Petri nets, Superscalar processors
40	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP DOI BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
40	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
40	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Scheduling of conditional branches using SSA form for superscalar/VLIW processors.	ICPADS	1996	DBLP DOI BibTeX RDF	conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
40	John-David Wellman, Edward S. Davidson	The resource conflict methodology for early-stage design space exploration of superscalar RISC processors.	ICCD	1995	DBLP DOI BibTeX RDF	resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
40	Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa	A superscalar RISC processor with pseudo vector processing feature.	ICCD	1995	DBLP DOI BibTeX RDF	superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
40	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
34	Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy	An evaluation of speculative instruction execution on simultaneous multithreaded processors.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading
34	Dean M. Tullsen, Susan J. Eggers, Henry M. Levy	Simultaneous Multithreading: Maximizing On-Chip Parallelism.	ISCA	1995	DBLP DOI BibTeX RDF
34	Omer Khan, Sandip Kundu	A model to exploit power-performance efficiency in superscalar processors via structure resizing.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	modeling, power
34	Shruti Patil, Venkatesan Muthukumar	Maximizing Resource Utilization by Slicing of Superscalar Architecture.	DSD	2008	DBLP DOI BibTeX RDF
34	Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
34	Thomas Kottke, Andreas Steininger	A Fail-Silent Reconfigurable Superscalar Processor.	PRDC	2007	DBLP DOI BibTeX RDF
34	Tejas Karkhanis, James E. Smith 0001	Automated design of application specific superscalar processors: an analytical approach.	ISCA	2007	DBLP DOI BibTeX RDF	performance model, analytical model, design optimization, energy model, application specific processors
34	Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith 0001	An approach for implementing efficient superscalar CISC processors.	HPCA	2006	DBLP DOI BibTeX RDF
34	Houman Homayoun, Ted H. Szymanski	Reducing the Instruction Queue Leakage Power in Superscalar Processors.	CCECE	2006	DBLP DOI BibTeX RDF
34	Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang 0006, Sotirios G. Ziavras	Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
34	Kuo-Su Hsiao, Chung-Ho Chen	An efficient wakeup design for energy reduction in high-performance superscalar processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	issue window, wakeup logic, low power, high performance
34	Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch	Design of superscalar processor with multi-bank register file.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
34	Ingomar Wenzel, Raimund Kirner, Peter P. Puschner, Bernhard Rieder	Principles of Timing Anomalies in Superscalar Processors.	QSIC	2005	DBLP DOI BibTeX RDF
34	Marc Epalza, Paolo Ienne, Daniel Mlynek	Adding Limited Reconfigurability to Superscalar Processors.	IEEE PACT	2004	DBLP DOI BibTeX RDF
34	Anne Bracy, Prashant Prahlad, Amir Roth	Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth.	MICRO	2004	DBLP DOI BibTeX RDF
34	Marc Epalza, Paolo Ienne, Daniel Mlynek	Dynamic Reallocation of Functional Units in Superscalar Processors.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
34	Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones	A framework for superscalar microprocessor correctness statements.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Microprocessor correctness, Commuting diagrams, Formal verification, Pipelines
34	Ryuichi Takahashi, Hajime Ohiwa	Situated Learning on FPGA for Superscalar Microprocessor Design Education.	SBCCI	2003	DBLP DOI BibTeX RDF
34	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
34	Santithorn Bunchua, D. Scott Wills, Linda M. Wills	Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
34	J. L. Silva, R. M. Costa, G. H. R. Jorge	RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip.	IWSOC	2003	DBLP DOI BibTeX RDF
34	Ing-Jer Huang, Ping-Huei Xie	Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
34	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
34	Christoforos E. Kozyrakis, David A. Patterson 0001	Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks.	MICRO	2002	DBLP DOI BibTeX RDF
34	Ravishankar Rao, Mark Oskin, Frederic T. Chong	HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.	HiPC	2002	DBLP DOI BibTeX RDF
34	Victor V. Zyuban, Peter M. Kogge	Inherently Lower-Power High-Performance Superscalar Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Low power microarchitecture, multicluster architecture, energy-efficient configurations, energy models
34	Joydeep Ray, James C. Hoe, Babak Falsafi	Dual use of superscalar datapath for transient-fault detection and recovery.	MICRO	2001	DBLP DOI BibTeX RDF
34	Miroslav N. Velev	Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors.	TACAS	2001	DBLP DOI BibTeX RDF
34	Seongwoo Kim, Arun K. Somani	SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors.	PRDC	2001	DBLP DOI BibTeX RDF
34	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen	System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
34	Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado	A Power Perspective of Value Speculation for Superscalar Microprocessors.	ICCD	2000	DBLP DOI BibTeX RDF