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Publication years (Num. hits)
2001-2005 (22) 2006-2007 (16) 2008-2011 (21) 2012-2014 (19) 2015-2016 (16) 2017-2018 (19) 2019-2020 (15) 2021-2022 (15) 2023-2024 (7)
Publication types (Num. hits)
article(30) inproceedings(118) phdthesis(2)
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The graphs summarize 30 occurrences of 28 keywords

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Found 150 publication records. Showing 150 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
160Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
119Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
107Rashed Zafar Bhatti, Monty Denneau, Jeff Draper 2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
80Hari Vijay Venkatanarayanan, Michael L. Bushnell A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
80Krzysztof Iniewski, R. Badalone, M. Lapointe, Marek Syrzycki SERDES Technology for Gigabit I/O Communications in Storage Area Networking. Search on Bibsonomy IWSOC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
80Yi Cai, S. A. Werner, G. J. Zhang, M. J. Olsen, Robert D. Brink Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
61Masashi Shimanouchi Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61Graham Hetherington, Richard Simpson Circular BIST testing the digital logic within a high speed Serdes. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61Takahiro J. Yamaguchi, Mani Soma, Masahiro Ishida, Hirobumi Musha, Louis Malarsie A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
58Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
41Wei-Zen Chen, Guan-Sheng Huang A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Ming-Ta Hsieh, Gerald E. Sobelman Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications. Search on Bibsonomy ISCAS (5) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Stephen K. Sunter, Aubin Roy, Jean-Francois Cote An Automated, Complete, Structural Test Solution for SERDES. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Jong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald 0001 A High Speed Reconfigurable Gate Array for Gigahertz Applications. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Thomas Palkert A Review of Current Standards Activities for High Speed Physical Layers, invited. Search on Bibsonomy IWSOC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39David Resnick Embedded Test for a new Memory-Card Architecture. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Navin K. Ramamoorthy, Jayabharath Reddy M, Vishwanath Muniyappa High Speed Serial Link Transmitter for 10Gig Ethernet Applications. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF SerDes I/O, tap co-efficients, Gigabits per second(Gbps), Equalization, Transmitter, ISI, CML
27Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
27Wei Cheng, Zhenhua Tan, Xiaoxing Gao, Guiran Chang, Jia Wen High Speed Serial Interface & Some Key Technology Research. Search on Bibsonomy ISECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SerDes, Bridge connection chip, High-speed serial interface
22Seoyoung Jang, Jaewon Lee, Gain Kim A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator. Search on Bibsonomy ICEIC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
22Ahmad Khairi, Yoel Krupnik, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Sabag, Vitali Rahinski, Idan Lotan, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky Grafi, Udi Virobnik, Dror Lazar, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Frank O'Mahony, Ariel Cohen 0001 A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22Dongwei Zou, Kezhu Song, Zhuo Chen, Chengyang Zhu, Tong Wu, Yuecheng Xu FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22Michael J. Degerstrom, Chad M. Smutzer, Patrick J. Zabinski, Barry K. Gilbert Inverting the SerDes Link Design Flow Process. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22J. M. Tharinda Rangana Jayawickrama, Subramaniam Thayaparan Use of SerDes to Reduce the Cost of Packaging of VLSIs. Search on Bibsonomy ICIIS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22Yajie Wu, Tianze Li, Zhuang Shao, Li Du, Yuan Du An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects. Search on Bibsonomy AICAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22Jun Chen, Fengyi Mei, Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. Search on Bibsonomy ASICON The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
22Li Ding, Jing Jin 0005, Jianjun Zhou A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
22Yoav Segal, Amir Laufer, Ahmad Khairi, Yoel Krupnik, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Saban, Vitali Rahinskj, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky, Udi Virobnik, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Ariel Cohen 0001 A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation. Search on Bibsonomy ISSCC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
22Seongyoon Kang, Jongsun Park 0001 Data Bus Inversion Encoding for Improving the Power Efficiency of SERDES-Containing Data Bus. Search on Bibsonomy ISOCC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
22Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Li Ding, Ke Wu, Jing Jin 0005, Jianjun Zhou An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Abdelrahman M. Sawaby, Abdelrahman M. Elshorbge, Omar T. Abdelhalim, Mahmoud A. Farghaly, Mahmoud Sherif Taha, Yehia Hamdy Yehia, Salma El-Sawy, Mohamed Samir Fouad, Hassan Mostafa A 10 Gb/s SerDes Transceiver. Search on Bibsonomy NILES The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Runze Chi, Junkun Chen, Youzhi Gu, Jiangfeng Wu, Yongzhen Chen A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm. Search on Bibsonomy ICTA The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Ping Lu A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFET. Search on Bibsonomy NorCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Ravi Shivnaraine, Marcus van Ierssel, Kamran Farzan, Dominic DiClemente, George Ng, Nanyan Wang, Javid Musayev, Gairik Dutta, Masumi Shibata, Arash Moradi, Haleh Vahedi, Manavi Farzad, Prabhnoor Kainth, Matt Yu, Nhat Nguyen, Jennifer Pham, Angus McLaren 11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Shiva Kiran, Ajay Balankutty, Yutao Liu, Rajeev Dokania, Hariprasath Venkataraman, Priya Wali, Stephen Kim, Yoel Krupnik, Ariel Cohen 0001, Frank O'Mahony A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Xiaozhe Wang, Lingzhi Su, Xiyuan Du, Yongzhen Chen, Jiangfeng Wu Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C. Search on Bibsonomy ASICON The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Miaomiao Wu, Zhengbin Pang, Fangxu Lv, Jianjun Shi, Heming Wang, Tao Liu, Dechao Lu, Zheng Wang An Adaptive Equalization Algorithm for High Speed SerDes. Search on Bibsonomy ASICON The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Jainaveen Sundaram, Srinivasan Gopal, Thomas P. Thomas, Edward Burton, Erika Ramirez A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects. Search on Bibsonomy ISQED The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. Search on Bibsonomy VLSID The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Raman Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta A Multi-Octave Frequency Range SerDes with a DLL Free Receiver. Search on Bibsonomy VDAT The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
22Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Yoel Krupnik, Yevgeny Perelman, Itamar Levin, Yosi Sanhedrai, Roee Eitan, Ahmad Khairi, Yizhak Shifman, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen 0001 112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar 0006, Gaurav Singh, Santosh Kumar Vishvakarma A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Deepanraj Thulasiraman, Javed S. Gaggatur A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications. Search on Bibsonomy Microelectron. J. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Andrés Quesada-Martínez, Javier Aparicio-Morales, José Campos-Araya, Alfonso Chacón-Rodríguez, Ronny García-Ramírez, Renato Rimolo-Donadio Evaluation of 8b/10b FPGA Encoder Implementations for SerDes Links. Search on Bibsonomy LASCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS. Search on Bibsonomy ICECS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Francesco Cosimi, Gabriele Ciarpi, Sergio Saponara Design and Analysis of RF/High-Speed SERDES in 28 nm CMOS Technology for Aerospace Applications. Search on Bibsonomy ApplePies The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. Search on Bibsonomy CICC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. Search on Bibsonomy ISCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Salem Abdennadher, Kyle Tripician, Senthil Singaravelu At Speed Testing Challenges and Solutions for 56Gbps and 112Gbps PAM4 SerDes. Search on Bibsonomy LATS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
22Zarraf Huda, Shovon Dey, Aaron Monai, Aurangozeb, Masum Hossain Affordable Sequence Decoding Techniques for High Speed SerDes. Search on Bibsonomy MWSCAS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
22Yi-Chieh Huang, Bo-Jiun Chen An 8b Injection-Locked Phase Rotator with Dynamic Multiphase Injection for 28/56/112Gb/s Serdes Application. Search on Bibsonomy ISSCC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
22Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. Search on Bibsonomy ISSCC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
22Yoel Krupnik, Yevgeny Perelman, Itamar Levin, Yosi Sanhedrai, Roee Eitan, Ahmad Khairi, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen 0001 112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process. Search on Bibsonomy VLSI Circuits The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
22Javed S. Gaggatur, Abhishek Chaturvedi A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application. Search on Bibsonomy VDAT The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
22Shi Xu, Zhang Luo, Mingche Lai, Zhengbin Pang, Renfa Li Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Wenhuan Luan, Ting Chen, Shuai Yuan 0005, Peijie Li, Ziqiang Wang, Xin Lin, Mao Li, Dengjie Wang, Hong Chen 0002 A 47mW Two-Dimensional Eye Opening Monitor for Multi-Protocol SerDes. Search on Bibsonomy MWSCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Vazgen Sh. Melikyan, Arshavir V. Matevosyan, Arman S. Petrosyan, Armen A. Martirosyan, Karen T. Khachikyan, Ruben H. Musayelyan, Arman S. Trdatyan, David K. Hakobyan High Quality Factor 5.0 Gbps CTLE Circuit for SERDES Serial Links. Search on Bibsonomy EWDTS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit. Search on Bibsonomy VLSI Circuits The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Heng Liu, Li Ding, Jing Jin 0005, Jianjun Zhou A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. Search on Bibsonomy ISCAS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Saket Srivastava, Peter Hobden Low Cost FPGA Implementation of a SPI over High Speed Optical SerDes. Search on Bibsonomy iSES The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Weifeng Fu, Qingsheng Hu, Rong Wang A 40 Gb/s PAM4 SerDes Receiver in 65nm CMOS Technology. Search on Bibsonomy CCECE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. Search on Bibsonomy VLSID The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Nitin Bansal, Rahul Gupta An NMOS Low Drop-out Voltage Regulator with -17dB Wide-Band Power Supply Rejection for SerDes in 22FDX. Search on Bibsonomy VLSID The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
22Markus Roman Müller Digital centric multi-gigabit SerDes design and verification. Search on Bibsonomy 2018   RDF
22Xuqiang Zheng Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process. Search on Bibsonomy 2018   RDF
22Xuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao 0004, Shuai Yuan 0005, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang 0001, Hanjun Jiang A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Ashkan Roshan-Zamir, Osama Elhadidy, Hae-Woong Yang, Samuel Palermo A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan 0005, Chun Zhang, Zhihua Wang 0001, Hanjun Jiang An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes. Search on Bibsonomy MWSCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Dongjun Park, Junsub Yoon, Jongsun Kim A low-power SerDes for high-speed on-chip networks. Search on Bibsonomy ISOCC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Taha Mehrabi, Kaamran Raahemifar Design of a time mode SerDes using differential pulse position modulation (DPPM). Search on Bibsonomy CCECE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Hongbing Tan, Haiyan Chen, Sheng Liu 0001, Xikun Ma, Yaqing Chi A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS. Search on Bibsonomy NCCET The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo 0003 A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes. Search on Bibsonomy NCCET The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices. Search on Bibsonomy VDAT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
22Shuai Yuan 0005, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang 0001 A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Kareem Ismail, Tawfik Ismail, Hassan Mostafa Design and implementation of CDR and SerDes for high speed optical communication networks using FPGA. Search on Bibsonomy ICTON The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Aaron Landy, Greg Stitt Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh 10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Hengzhou Yuan, Yang Guo 0003, Yao Liu, Bin Liang, Qian-cheng Guo, Jia-wei Tan A low-jitter self-biased phase-locked loop for SerDes. Search on Bibsonomy ISOCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi SERDES external loopback test using production parametric-test hardware. Search on Bibsonomy ITC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. Search on Bibsonomy VLSID The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
22Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Fanta Chen, Jen-Ming Wu, Mau-Chung Frank Chang 40-Gb/s 0.7-V 2: 1 MUX and 1: 2 DEMUX with Transformer-Coupled Technique for SerDes Interface. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Chunmei Hu, Shuming Chen, Pengcheng Huang, Yao Liu, Jianjun Chen Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. Search on Bibsonomy ICEAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Ke Huang 0003, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang 0001 A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. Search on Bibsonomy CICC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng 56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. Search on Bibsonomy VLSIC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Rigoberto Bracamontes-Salazar, Esdras Juárez-Hernández, Federico Lobato-Lopez, Esteban Martinez Guerrero CMOS amplifier with self-correction offset for SerDes applications. Search on Bibsonomy LATS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Fangxu Lv, Xuqiang Zheng, Ziqiang Wang, Jianye Wang, Fule Li A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology. Search on Bibsonomy ASICON The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Nivedita Jaiswal, Radheshyam Gamad Three Levels Interconnect Signaling in On-Chip High Speed SerDes Transceiver for Multi-Module SoC Communication. Search on Bibsonomy ICCCT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
22Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang 0001, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Yujie Zang A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface. Search on Bibsonomy J. Commun. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. Search on Bibsonomy CICC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Ke Huang 0003, Ziqiang Wang, Xuqiang Zheng, Chun Zhang, Zhihua Wang 0001 A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology. Search on Bibsonomy CICC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Anant Singh, Dario Albino Carnelli, Altay Falay, Klaas L. Hofstra, Fabio Licciardello, Kia Salimi, Hugo Santos, Amin Shokrollahi, Roger Ulrich, Christoph Walter, John Fox, Peter Hunt, John Keay, Richard Simpson, Andrew Stewart, Giuseppe Surace, Harm S. Cronie 26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology. Search on Bibsonomy ISSCC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang 0001, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong 2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
22Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
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