Search results for "SoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
91	Soo Ho Chang, Soo Dong Kim	Reuse-based Methodology in Developing System-on-Chip (SoC).	SERA	2006	DBLP DOI BibTeX RDF
64	Bing Guo, Yan Shen, Yue Huang, Zhishu Li	A Novel Discrete Hopfield Neural Network Approach for Hardware-Software Partitioning of RTOS in the SoC.	EUC Workshops	2006	DBLP DOI BibTeX RDF	SoC, RTOS, Hopfield neural network, Hardware-software partitioning
64	Yves Mathys, André Chátelain	Verification strategy for integration 3G baseband SoC.	DAC	2003	DBLP DOI BibTeX RDF	3G baseband, verification, architecture, SoC
62	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
59	Anil Deshpande	Verification of IP-Core Based SoC's.	ISQED	2008	DBLP DOI BibTeX RDF	Verification, SoC, Moore's Law
56	Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu	SoC-level risk assessment using FMEA approach in system design with SystemC.	SIES	2009	DBLP DOI BibTeX RDF
56	Du Wan Cheun, Tae Kwon Yu, Soo Ho Chang, Soo Dong Kim	A Technical Assessment of SoC Methodologies and Requirements for a Full-Blown Methodology.	ICCSA (2)	2006	DBLP DOI BibTeX RDF
52	Sandeep Kumar Goel, Erik Jan Marinissen	SOC test architecture design for efficient utilization of test bandwidth.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization
52	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy	On Concurrent Test of Core-Based SOC Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	concurrent SOC test, pin mapping, 2-dimensional bin-packing, test scheduling
51	Yen-Kuang Chen, Sun-Yuan Kung	Trend and Challenge on System-on-a-Chip Designs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	SoC design trend, SoC design challenge, VLSI, SoC, system-on-a-chip
51	Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Chin-Long Wey	PrSoC: Programmable System-on-chip (SoC) for silicon prototyping.	ISCAS	2008	DBLP DOI BibTeX RDF
51	Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu	STEAC: A Platform for Automatic SOC Test Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
47	Anuja Sehgal, Krishnendu Chakrabarty	Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
47	Wolfgang Mueller, Yves Vanderperren	UML and model-driven development for SoC design.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	simulation, UML, SoC, tools, SystemC, UML profiles, ESL design
47	Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho	Modeling and analysis of the system bus latency on the SoC platform.	SLIP	2006	DBLP DOI BibTeX RDF	multi-layer bus, system bus, SoC, latency, platform
47	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
47	Frédéric Flouvat, Jean-François N'guyen Van Soc, Elise Desmier, Nazha Selmaoui-Folcher	Domain-driven co-location mining - Extraction, visualization and integration in a GIS.	GeoInformatica	2015	DBLP DOI BibTeX RDF
47	Martin P. Calasan, Nikola Soc, Vladan Vujicic, Gojko Joksimovic, Chen Hao, Qianglong Wang, Xing Wang	Review of marine current speed and power coefficient - Mathematical models.	MECO	2015	DBLP DOI BibTeX RDF
46	Vincenzo Rana, David Atienza, Marco D. Santambrogio, Donatella Sciuto, Giovanni De Micheli	A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
46	Wei-Tek Tsai, Yinong Chen, Xin Sun 0003	Designing a Service-Oriented Computing Course for High Schools.	ICEBE	2007	DBLP DOI BibTeX RDF
45	Subir K. Roy	Top Level SOC Interconnectivity Verification Using Formal Techniques.	MTV	2007	DBLP DOI BibTeX RDF
45	Tun Li, Sikun Li, Jinshan Yu, Yang Guo 0003	A Novel Collaborative Verification Environment for SoC Co-Verification.	CSCWD	2007	DBLP DOI BibTeX RDF
45	Qiang Xu 0001, Nicola Nicolici	Modular SOC testing with reduced wrapper count.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
45	Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron	LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction.	ISQED	2003	DBLP DOI BibTeX RDF
45	Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi 0001, Michael Torla, Catherine H. Gebotys	Special Session: Security on SoC.	ISSS	2002	DBLP DOI BibTeX RDF	sequence charts, simulation, validation methodology
45	Kazutoshi Wakabayashi, Takumi Okamoto	C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
44	Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch	HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, VLSI, system-on-chip, multi-core, surveillance, MPEG-4
44	Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis	SoC Design Skills: Collaboration Builds a Stronger SoC Design Team.	MSE	2001	DBLP DOI BibTeX RDF
43	C. P. Ravikumar, Jari Nurmi	Conference Reports.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	Melvin Breuer, SOC 2006, SoC design, ITC
43	Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho	On-Chip Bus Modeling for Power and Performance Estimation.	SAMOS	2007	DBLP DOI BibTeX RDF	bus modeling, bus latency, SoC, on-chip bus
42	Chih-Pin Su, Cheng-Wen Wu	A Graph-Based Approach to Power-Constrained SOC Test Scheduling.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test integration, test scheduling, test access mechanism (TAM), SOC testing, test power, system-on-chip (SOC)
41	Cheol-Hong Moon, Sung-Oh Kim	An SoC System for the Image Grabber Capable of 2D Scanning.	ICNC (2)	2006	DBLP DOI BibTeX RDF	IMAGE IP, Perpendicular Coordinate Robot IP, TFT-LCD IP, SoC
40	Stefan Thanheiser, Lei Liu 0020, Hartmut Schmeck	SimSOA: an approach for agent-based simulation and design-time assessment of SOC-based IT systems.	SAC	2009	DBLP DOI BibTeX RDF	service-oriented computing (SOC), service-oriented architectures (SOA), agent-based simulation
40	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
40	Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun	A 2.6 µW sub-threshold mixed-signal ECG SoC.	ISLPED	2009	DBLP DOI BibTeX RDF	sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
40	Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He 0001, Zhixiong Zhou, Ting Lei	Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC.	DELTA	2008	DBLP DOI BibTeX RDF	SoC system testing, genetic and evolutionary algorithm, design verification
40	Cheol-Hong Moon, Dong-Young Jang, Jong-Nam Choi	An SoC System for Real-Time Moving Object Detection.	ICIC (1)	2007	DBLP DOI BibTeX RDF	SoC IP, Image processing, Real-time, Moving Object Detection
40	Tse-Chen Yeh, Tsung-Yu Ho, Hung-Yu Chen, Ing-Jer Huang	SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics.	EUC	2007	DBLP DOI BibTeX RDF	SystemC modeling, 3D graphics SoC, design space exploration, transaction-level modeling
40	Jia-Ming Chen, Chih-Hao Chang, Shau-Yin Tseng, Jenq Kuen Lee, Wei-Kuan Shih	Power Aware H.264/AVC Video Player on PAC Dual-Core SoC Platform.	EUC	2006	DBLP DOI BibTeX RDF	Dual-Core SoC, H.264/AVC, Power-aware, DVFS
40	Tim Kogel, Heinrich Meyr	Heterogeneous MP-SoC: the solution to energy-efficient signal processing.	DAC	2004	DBLP DOI BibTeX RDF	energy efficiency, network-on-chip, signal processing, design space exploration, MP-SoC
40	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
40	Rainer Dorsch, Ramón Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer	Adapting an SoC to ATE Concurrent Test Capabilities.	ITC	2002	DBLP DOI BibTeX RDF	ATE, SoC Test, Concurrent Test, Test Resource Partitioning
40	Mahesh Mehendale	Challenges in the Design of Embedded Real-time DSP SoCs.	VLSI Design	2004	DBLP DOI BibTeX RDF
39	Ozgur Sinanoglu, Erik Jan Marinissen	Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.	DATE	2008	DBLP DOI BibTeX RDF
39	Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale	Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.	IOLTS	2007	DBLP DOI BibTeX RDF
39	Cheol-Hong Moon, Young-Soo Roo, Hwa-Young Kim	An SoC Embedded System Implementation Using an Array Sensor.	FSKD (3)	2007	DBLP DOI BibTeX RDF
39	Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi	A UML Based System Level Failure Rate Assessment Technique for SoC Designs.	VTS	2007	DBLP DOI BibTeX RDF
39	Miguel Ángel Cristín Valdez, Jaime Adrián Orozco Valera, María Jojutla Olimpia Pacheco Arteaga	Estimating Soc in Lead-Acid Batteries Using Neural Networks in a Microcontroller-Based Charge-Controller.	IJCNN	2006	DBLP DOI BibTeX RDF
39	Terence Chan	RaceCheck: A Race Logic Audit Program For SoC Designs.	APCCAS	2006	DBLP DOI BibTeX RDF
39	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud	SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers.	DAC	2006	DBLP DOI BibTeX RDF	LNA optimization, low noise amplifier, analog synthesis
39	Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo	Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design.	RTCSA	2005	DBLP DOI BibTeX RDF	Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System
39	Mohsen Nahvi, André Ivanov	Indirect test architecture for SoC testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
39	Jinyu Zhan, Nan Sang, Guangze Xiong	Formal Co-verification for SoC Design with Colored Petri Net.	ICESS	2004	DBLP DOI BibTeX RDF
39	Keon-Myung Lee, Bong Ki Sohn, Jong Tae Kim, Seung Wook Lee, Ji Hyong Lee, Jae Wook Jeon, Jundong Cho	An SoC-Based Context-Aware System Architecture.	KES	2004	DBLP DOI BibTeX RDF
39	Imed Moussa, Thierry Grellier, Giang Nguyen	Exploring SW Performance Using SoC Transaction-Level Modeling.	DATE	2003	DBLP DOI BibTeX RDF
39	Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee	Infrastructure for Education and Research of SOC/IP in Taiwan.	MSE	2003	DBLP DOI BibTeX RDF
38	Steve Leibson, Grant Martin	Design and verification of complex SoC with configurable, extensible processors.	SoCC	2008	DBLP DOI BibTeX RDF
37	K. Schultz, Ketan Paranjape	SOC Debug Challenges and Tools.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
37	Sanghun Lee, Chanho Lee	A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
37	Shaojun Wei	Key technologies of system on chip design.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	IC vendor software, SoC, hardware/software co-design, energy-aware design
37	Limin Liu, Ping Yan	A Bumpless Switching Scheme for Dynamic Reconfiguration.	CDVE	2007	DBLP DOI BibTeX RDF	bumpless switching, SoC, dynamic reconfiguration
37	Chris Rowen, Steve Leibson	Flexible architectures for engineering successful SOCs.	DAC	2004	DBLP DOI BibTeX RDF	processor cores, MPSOC, RISC, RTL, SOC
37	Partha Pratim Pande, Cristian Grecu, André Ivanov	High-Throughput Switch-Based Interconnect for Future SoCs.	IWSOC	2003	DBLP DOI BibTeX RDF	SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture
36	Victor Grimblatt, Chip-Hong Chang, Ricardo Reis 0001, Anupam Chattopadhyay, Andrea Calimera (eds.)	VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2022	DBLP DOI BibTeX RDF
36	Moreno Bragaglio, Samuele Germiniani, Graziano Pravadelli	Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Zhao Han, Gabriel Rutsch, Deyan Wang, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker	Transformative Hardware Design Following the Model-Driven Architecture Vision.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Ming Ming Wong, Lu Chen, Anh Tuan Do	An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Thiago Santos Copetti, Tobias Gemmeke, Letícia Maria Bolzani Pöhls	A DfT Strategy for Detecting Emerging Faults in RRAMs.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Sarah Azimi, Corrado De Sio, Andrea Portaluri, Luca Sterpone	Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle	FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Shubham Rai, Nishant Gupta, Abhiroop Bhattacharjee, Ansh Rupani, Michael Raitza, Jens Trommer, Thomas Mikolajick, Akash Kumar 0001	END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	J. Gasquez, Bastien Giraud, P. Boivin, Y. Moustapha-Rabault, Vincenzo Della Marca, Jean-Michel Walder, Jean-Michel Portal	A Regulated Sensing Solution Based on a Self-reference Principle for PCM + OTS Memory Array.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Parya Zolfaghari, Sébastien Le Beux	Design of a Reconfigurable Optical Computing Architecture Using Phase Change Material.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari	Low-Overhead Early-Stopping Policies for Efficient Random Forests Inference on Microcontrollers.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii	On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets.	VLSI-SoC (Selected Papers)	2021	DBLP DOI BibTeX RDF
36	Tutu Ajayi, Sumanth Kamineni, Morteza Fayazi, Yaswanth K. Cherivirala, Kyumin Kwon, Shourya Gupta, Wenbo Duan, Jeongsup Lee, Chien-Hen Chen, Mehdi Saligane, Dennis Sylvester, David T. Blaauw, Ronald Dreslinski Jr., Benton H. Calhoun, David D. Wentzloff	Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.	VLSI-SoC (Selected Papers)	2020	DBLP DOI BibTeX RDF
36	Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano	Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
36	Ricardo Reis 0001, Manfred Glesner	VLSI-SoC: An Enduring Tradition.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
36	Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez 0001, Federico Venini	Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.	VLSI-SoC (Selected Papers)	2016	DBLP DOI BibTeX RDF
36	Manikandan Pandiyan, Geetha Mani	Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip.	VLSI-SoC (Selected Papers)	2015	DBLP DOI BibTeX RDF
36	Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang 0010, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert	High Performance SoC Design Using Magnetic Logic and Memory.	VLSI-SoC (Selected Papers)	2011	DBLP DOI BibTeX RDF
36	Christian Piguet, Ricardo Reis 0001, Dimitrios Soudris (eds.)	VLSI-SoC: Design Methodologies for SoC and SiP - 16th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers	VLSI-SoC (Selected Papers)	2010	DBLP DOI BibTeX RDF
36	Laura Frigerio, Kellie Marks, Argy Krikelis	Timed Coloured Petri Nets for Performance Evaluation of DSP Applications: The 3GPP LTE Case Study.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Alessandro Cilardo, Nicola Mazzocca	Time Efficient Dual-Field Unit for Cryptography-Related Processing.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Ian O'Connor, Ilham Hassoune, David Navarro	Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Kostas Siozios, Dimitrios Soudris	A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Tilo Meister, Jens Lienig, Gisbert Thomke	Universal Methodology to Handle Differential Pairs during Pin Assignment.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Andre Guntoro, Manfred Glesner	A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani	Comparison of Two Autonomous AC-DC Converters for Piezoelectric Energy Scavenging Systems.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Vasilis F. Pavlidis, Eby G. Friedman	Physical Design Issues in 3-D Integrated Technologies.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Nikolas Kroupis, Dimitrios Soudris	Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Christophe Escriba, Remy Fulcrand, Philippe Artillan, David Jugieu, Aurélien Bancaud, Ali Boukabache, Anne Marie Gué, Jean-Yves Fourniols	Trapping Biological Species in a Lab-on-Chip Microsystem: Micro Inductor Optimization Design and SU8 Process.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Vassilios Vonikakis, Chryssanthi Iakovidou, Ioannis Andreadis	Real-Time Biologically-Inspired Image Exposure Correction.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos	Timing Error Detection and Correction by Time Dilation.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Vasilios Kalenteridis, Konstantinos Papathanasiou, Stylianos Siskos	Analysis and Design of Charge Pumps for Telecommunication Applications.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re	On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.	VLSI-SoC (Selected Papers)	2008	DBLP DOI BibTeX RDF
36	Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz	Optimizing SOC Test Resources Using Dual Sequences.	VLSI-SoC (Selected Papers)	2003	DBLP DOI BibTeX RDF
36	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi	An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms.	VLSI-SOC	2001	DBLP BibTeX RDF
36	Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski	Built-in Test of Analog Non-Linear Circuits in a SOC Environment.	VLSI-SOC	2001	DBLP BibTeX RDF