Search results for "Sub-Vt"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Joseph F. Ryan 0002, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
15	Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons 0001, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery	Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.	ISLPED	2019	DBLP DOI BibTeX RDF
13	Steven C. Jocke, Jonathan F. Bolus, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun	A 2.6 µW sub-threshold mixed-signal ECG SoC.	ISLPED	2009	DBLP DOI BibTeX RDF	sub-threshold SoC, sub-threshold operation, system on chip, electrocardiogram
10	Amit Agarwal 0001, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy 0001	A process-tolerant cache architecture for improved yield in nanoscale technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
8	David Zooker, Yoav Weizman, Alexander Fish, Osnat Keren	Silicon Proven 1.29 μm × 1.8 μm 65nm Sub-Vt Optical Sensor for Hardware Security Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
8	David Zooker Zabib, Alexander Fish, Osnat Keren, Yoav Weizman	Compact Sub-Vt Optical Sensor for the Detection of Fault Injection in Hardware Security Applications.	NTMS	2019	DBLP DOI BibTeX RDF
8	Jiangyi Li, Pavan Kumar Chundi, Sung Kim, Zhewei Jiang, Minhao Yang, Joonseong Kang, Seungchul Jung, Sang Joon Kim, Mingoo Seok	A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit.	ESSCIRC	2018	DBLP DOI BibTeX RDF
8	Wei Jin 0004, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok	Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
8	Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues	A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
8	Yongtae Kim, Peng Li 0001	A 0.38 V near/sub-VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process.	IET Circuits Devices Syst.	2013	DBLP DOI BibTeX RDF
8	S. M. Yasser Sherazi, Joachim Neves Rodrigues, Omer Can Akgun, Henrik Sjöland, Peter Nilsson 0001	Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
8	Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues	A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
8	Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues	Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.	ESSCIRC	2013	DBLP DOI BibTeX RDF
8	Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli	A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.	NEWCAS	2013	DBLP DOI BibTeX RDF
8	Chris Winstead, Joachim Neves Rodrigues	Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-VT Operation.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
8	Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg	An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing.	VLSI-SoC (Selected Papers)	2012	DBLP DOI BibTeX RDF
8	S. M. Yasser Sherazi, Peter Nilsson 0001, Henrik Sjöland, Joachim Neves Rodrigues	A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS.	ICECS	2012	DBLP DOI BibTeX RDF
8	Pascal Andreas Meinerzhagen, Oskar Andersson, Babak Mohammadi, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues	A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.	ESSCIRC	2012	DBLP DOI BibTeX RDF
8	Pascal Andreas Meinerzhagen, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues	Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2011	DBLP DOI BibTeX RDF
8	Oskar Andersson, S. M. Yasser Sherazi, Joachim Neves Rodrigues	Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS.	NORCHIP	2011	DBLP DOI BibTeX RDF
8	Pascal Andreas Meinerzhagen, Oskar Andersson, S. M. Yasser Sherazi, Andreas Peter Burg, Joachim Neves Rodrigues	Synthesis strategies for sub-VT systems.	ECCTD	2011	DBLP DOI BibTeX RDF
8	S. M. Yasser Sherazi, Peter Nilsson 0001, Omer Can Akgun, Henrik Sjöland, Joachim Neves Rodrigues	Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain.	ISCAS	2011	DBLP DOI BibTeX RDF
8	Joachim Neves Rodrigues, Omer Can Akgun, Viktor Öwall	A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
8	Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Anantha P. Chandrakasan	A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
8	Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall	Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding.	PATMOS	2009	DBLP DOI BibTeX RDF
8	Joyce Kwong, Yogesh K. Ramadass, Naveen Verma, Markus Koesler, Korbinian Huber, Hans Moormann, Anantha P. Chandrakasan	A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter.	ISSCC	2008	DBLP DOI BibTeX RDF
8	Naveen Verma, Anantha P. Chandrakasan	A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy.	ISSCC	2007	DBLP DOI BibTeX RDF
6	Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici	Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.	PATMOS	2008	DBLP DOI BibTeX RDF	Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations