Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Kelly D. Larson |
Translation of an existing VMM-based SystemVerilog testbench to OVM. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
OVM, VMM, testbenches, SystemVerilog |
96 | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
89 | Tom Fitzpatric |
System Verilog for VHDL Users. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
78 | Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji |
SystemC and SystemVerilog: Where do They Fit? Where are They Going? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
68 | Clifford E. Cummings |
SystemVerilog implicit port enhancements accelerate system design & verification. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
*, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog |
60 | Doron Bustan, John Havlicek |
Some Complexity Results for SystemVerilog Assertions. |
CAV |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Alexander Krupp, Wolfgang Müller 0003 |
Classification trees for random tests and functional coverage. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil |
Synthesis of synchronous assertions with guarded atomic actions. |
MEMOCODE |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Brian Bailey |
Was it worth the wait? Yes! |
IEEE Des. Test Comput. |
2006 |
DBLP DOI BibTeX RDF |
verification, formal verification, design reuse, testbench, SystemVerilog |
42 | Albert Chiang, Wei-Hua Han, Bhanu Kapoor |
Validating physical access layer of WiMAX using SystemVerilog. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Hai H. Wang, Shengchao Qin, Jun Sun 0001, Jin Song Dong |
Realizing Live Sequence Charts in SystemVerilog. |
TASE |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Yingpan Wu, Lixin Yu, Wei Zhuang, Jianyong Wang |
A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit. |
ACIS-ICIS |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang |
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
36 | A. Bernstein, M. Burton, Frank Ghenassia |
How to bridge the abstraction gap in system level modeling and design. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Kausik Datta, Partha Pratim Das |
Assertion Based Verification Using HDVL. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). |
GPCE |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
26 | Michael Siegel, Adriana Maggiore, Christian Pichler |
Untwist your brain: efficient debugging and diagnosis of complex assertions. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
SystemVerilog assertions, debugging, assertions, fault localization, functional verification, root cause analysis |
26 | Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch |
Building a standard ESL design and verification methodology: is it just a dream? |
DAC |
2006 |
DBLP DOI BibTeX RDF |
modeling rapid hardware prototyping, design, verification, methodology, systemC, RTL, ESL, C/C++, systemVerilog |
26 | Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee |
Formal hardware specification languages for protocol compliance verification. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language |
26 | James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois |
ESys.Net: a new solution for embedded systems modeling and simulation. |
LCTES |
2004 |
DBLP DOI BibTeX RDF |
CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog |
24 | Bilal Majeed, Conor Ryan, Jack McEllin, Ayman Youssef, Douglas Mota Dias, Aidan Murphy, Samuel Carvalho |
Evolving Behavioural Level Sequence Detectors in SystemVerilog Using Grammatical Evolution. |
ICAART (3) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Wei-Ting Yeh, Chung-Lun Chang, Shang-Chih Yin, Chien-Hung Tsai |
Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. |
GCCE |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan |
Grammatical Evolution of Complex Digital Circuits in SystemVerilog. |
SN Comput. Sci. |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Christos Sapsanis, Martin Villemur, Andreas G. Andreou |
Real Number Modeling of a SAR ADC behavior using SystemVerilog. |
SMACD |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviades A. Hatzopoulos |
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog. |
J. Electron. Test. |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan |
Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with SystemVerilog. |
EuroGP |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Yuichi Kamina, Keisuke Iwai, Takashi Matsubara 0002, Takakazu Kurokawa |
A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference. |
CANDAR (Workshops) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif, Wasi Haider Butt |
A model-driven framework for design and verification of embedded systems through SystemVerilog. |
Des. Autom. Embed. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
UVM-based Verification of a Digital PLL Using SystemVerilog. |
PATMOS |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model. |
DSD |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Mina Louis, Mohamed Dessouky, Ashraf Salem |
PLL Real Number Modeling in SystemVerilog. |
SMACD |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Juan-José Crespo, German Maglione Mathey, José L. Sánchez 0002, Francisco J. Alfaro-Cortes, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001 |
Methodology for Decoupled Simulation of SystemVerilog HDL Designs. |
HPCS |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Design of a Digital PLL Real Number Model Using SystemVerilog. |
MOCAST |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Athanasios Mekras, Alkiviadis A. Hatzopoulos |
Design of a SystemVerilog-Based VCO Real Number Model. |
MOCAST |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos |
UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. |
PATMOS |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe |
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. |
ASYNC |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Michael Bedford Taylor |
Basejump STL: systemverilog needs a standard template library for hardware design. |
DAC |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Efficiency evaluation of a SystemVerilog-based real number model. |
MOCAST |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif |
Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. |
Des. Autom. Embed. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang |
PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. |
Comput. Informatics |
2016 |
DBLP BibTeX RDF |
|
24 | Oriol Arcas-Abella, Nehir Sönmez |
Bluespec SystemVerilog. |
FPGAs for Software Programmers |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Aamir M. Khan, Muhammad Rashid |
Generation of SystemVerilog Observers from SysML and MARTE/CCSL. |
ISORC |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Rashid, Muhammad Waseem Anwar, Farooque Azam |
Expressing embedded systems verification aspects at higher abstraction level - SystemVerilog in Object Constraint Language (SVOCL). |
SysCon |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Jaeha Kim |
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky |
SystemVerilog assertion debugging: A visualization and pattern matching model. |
PACRIM |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Jeremy Ridgeway |
Performance of a SystemVerilog Sudoku Solver with VCS. |
MTV |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Sara Marconi, Elia Conti, Jorgen Christiansen, Pisana Placidi |
Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications. |
ISSE |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Sara Marconi, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, Tomasz Hemperek |
A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. |
ApplePies |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Yunzhong Zhu, Tao Li, Jingpeng Guo, Haiyang Zhou, Fangfa Fu |
A novel low-cost interface design for SystemC and SystemVerilog Co-simulation. |
ASICON |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Ning Zhou, Xinyan Gao, Jinzhao Wu, Jianchao Wei, Dakui Li |
Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions. |
J. Appl. Math. |
2014 |
DBLP DOI BibTeX RDF |
|
24 | An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou |
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. |
ACM Trans. Design Autom. Electr. Syst. |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Abhishek Jain 0003, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar |
Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. |
CoRR |
2014 |
DBLP BibTeX RDF |
|
24 | Jaeha Kim, Si-Jung Yang, Ji-Eun Jang |
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. |
CICC |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Xinyan Gao, Ning Zhou, Jinzhao Wu, Dakui Li |
Wu's Characteristic Set Method for SystemVerilog Assertions Verification. |
J. Appl. Math. |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Dave Rich |
The unique challenges of debugging design and verification code jointly in SystemVerilog. |
FDL |
2013 |
DBLP BibTeX RDF |
|
24 | Jonathan Bromley |
If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. |
FDL |
2013 |
DBLP BibTeX RDF |
|
24 | Kaiming Ho |
SystemVerilog: The new standard. |
FDL |
2013 |
DBLP BibTeX RDF |
|
24 | Ji-Eun Jang, Si-Jung Yang, Jaeha Kim |
Event-driven simulation of Volterra series models in SystemVerilog. |
CICC |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim |
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. |
DAC |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang 0006 |
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. |
IEEE Des. Test Comput. |
2012 |
DBLP DOI BibTeX RDF |
|
24 | An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou |
A formal method to improve SystemVerilog functional coverage. |
HLDVT |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Sangook Moon |
Systemverilog-based approach of a design of multiplication server farms. |
ICUFN |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Sergio H. M. Durand, Vanderlei Bonato |
A tool to support Bluespec SystemVerilog coding based on UML diagrams. |
IECON |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim |
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. |
CICC |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Jomu George Mani Paret, Otmane Aït Mohamed |
Modeling discrete event system with distributions using SystemVerilog. |
ISCAS |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Dominic Richards, David R. Lester |
A monadic approach to automated reasoning for Bluespec SystemVerilog. |
Innov. Syst. Softw. Eng. |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Brian Keng, Sean Safarpour, Andreas G. Veneris |
Automated debugging of SystemVerilog assertions. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Hans Eveking, Tobias Dornes, Martin Schweikert |
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. |
HLDVT |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Ryuichi Takahashi, Yoshiyasu Takefuji |
SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. |
MSE |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song |
Design and verification of an application-specific PLD using VHDL and SystemVerilog. |
ASICON |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. |
DIFTS@FMCAD |
2011 |
DBLP BibTeX RDF |
|
24 | Arash Saifhashemi, Peter A. Beerel |
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. |
CPA |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Myoung-Keun You, Gi-Yong Song |
SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Bahram Hakhamaneshi, Behnam S. Arad |
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog. |
CATA |
2010 |
DBLP BibTeX RDF |
|
24 | Alexander Bol, Wolfgang Müller 0003, Alexander Krupp |
Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. |
MBMV |
2010 |
DBLP BibTeX RDF |
|
24 | David Rich |
A Solution to the Lack of Multiple Inheritance in SystemVerilog. |
FDL |
2010 |
DBLP BibTeX RDF |
|
24 | Dominic Richards, David R. Lester |
A Prototype Embedding of Bluespec SystemVerilog in the PVS Theorem Prover. |
NASA Formal Methods |
2010 |
DBLP BibTeX RDF |
|
24 | Chengjie Zang, Shinji Kimura |
Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Ivan Kastelan, Zoran Krajacevic |
Synthesizable SystemVerilog Assertions as a Methodology for SoC. |
ECBS-EERC |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Robert C. Page, Sakar Jain |
Verification of the CoreNet Fabric with SystemVerilog. |
MTV |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson |
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Ka Lok Man |
PAFSV: A process algebraic framework for SystemVerilog. |
IMCSIT |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Ronald W. Mehler |
SystemVerilog Maximum Performance Maneuvers. |
MSV |
2008 |
DBLP BibTeX RDF |
|
24 | Tingjun Wen, Tadeusz Kwasniewski |
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. |
BMAS |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi |
SystemVerilog: Interface Based Design. |
FDL |
2004 |
DBLP BibTeX RDF |
|
24 | Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Müller 0003 |
The Formal Simulation Semantics of SystemVerilog. |
FDL |
2004 |
DBLP BibTeX RDF |
|
24 | Phil Moorby |
Design for Verification with SystemVerilog. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
24 | David I. Rich |
The Evolution of SystemVerilog. |
IEEE Des. Test Comput. |
2003 |
DBLP BibTeX RDF |
|
18 | Daniel Gajski, Todd M. Austin, Steve Svoboda |
What input-language is the best choice for high level synthesis (HLS)? |
DAC |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Perry Alexander |
Rosetta: Standardization at the System Level. |
Computer |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough |
Instrumenting AMS assertion verification on commercial platforms. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion |
18 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
18 | Christian Dax, Felix Klaedtke, Martin Lange |
On Regular Temporal Logics with Past, . |
ICALP (2) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Inline Assertions - Embedding Formal Properties in a Test Bench. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Alon Gluska, Lior Libis |
Shortening the verification cycle with synthesizable abstract models. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
verification, logic design, abstract modeling |
18 | Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks |
H.264 Decoder: A Case Study in Multiple Design Points. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Nathaniel J. August |
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
pre-silicon, validation, mixed-signal |
18 | Dennis Brophy |
IEEE Market-Oriented Standards Process and the EDA Industry. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi |
Heterogeneous Behavioral Hierarchy Extensions for SystemC. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|