Search results for "TSUM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	Multiple-Valued Product-of-Sums Expression with Truncated Sum.	ISMVL	1997	DBLP DOI BibTeX RDF
77	Satoshi Kubo	Tsum Tsum "Frozen".	SIGGRAPH Computer Animation Festival	2015	DBLP DOI BibTeX RDF
54	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
54	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
54	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	On Input Permutation Technique for Multiple-Valued Logic Synthesis.	ISMVL	1995	DBLP DOI BibTeX RDF	input permutation technique, multiple-valued logic synthesis, multiple valued sum of products expressions, TSUM, minimal sum of products expressions, permuted logic values, randomly generated functions, input permutation, output permutation, minimization times, window literals, sum of products expressions, set literals, logic design, set theory, multivalued logic
47	A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
39	Jieying Chen, Jia-Yu Pan, Christos Faloutsos, Spiros Papadimitriou	TSum: fast, principled table summarization.	AdKDD@KDD	2013	DBLP DOI BibTeX RDF
39	Noboru Takagi, Kyoichi Nakashima	Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and Literals.	ISMVL	2002	DBLP DOI BibTeX RDF
39	Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and Variables.	ISMVL	1993	DBLP DOI BibTeX RDF
23	Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato	An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations.	ISMVL	2000	DBLP DOI BibTeX RDF	multilevel circuits, various operations, genetic algorithm, logic synthesis
23	Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato	Multiple-Valued Logic Minimization by Genetic Algorithms.	ISMVL	1997	DBLP DOI BibTeX RDF
23	Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono	A Necessary and Sufficient Condition for Lukasiewicz Logic Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design