Search results for "TSV"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
182	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
138	Sudeep Pasricha	Exploring serial vertical interconnects for 3D ICs.	DAC	2009	DBLP DOI BibTeX RDF	serial interconnect, VLSI, networks on chip, 3D ICs
106	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
99	Koichi Sato, J. K. Aggarwal	Tracking soccer players using broadcast TV images.	AVSS	2005	DBLP DOI BibTeX RDF
83	Zongwu Tang	Efficient design practices for thermal management of a TSV based 3D IC system.	ISPD	2010	DBLP DOI BibTeX RDF	thermal gradient, placement, design rule, TSV
79	Tae-Yong Kim 0002, Ulrich Neumann	A Thin Shell Volume for Modeling Human Hair.	CA	2000	DBLP DOI BibTeX RDF
67	Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim	Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.	SLIP	2009	DBLP DOI BibTeX RDF	wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via
64	Khaled Salah 0001	A TSV to TSV, A TSV to Metal interconnects, and A TSV to active device coupling capacitance: Analysis and recommendations.	DTIS	2015	DBLP DOI BibTeX RDF
48	Caleb Serafy, Ankur Srivastava 0001	TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
48	Khaled Salah 0001, Yehea I. Ismail	Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV.	ISCAS	2015	DBLP DOI BibTeX RDF
48	Weng Hong Teh, Raymond Caramto, Jamal Qureshi, Sitaram Arkalgud, M. O'Brien, T. Gilday, Kou Maekawa, T. Saito, Kouichi Maruyama, Thenappan Chidambaram, Wei Wang 0003, David Marx, David Grant, Russ Dudley	A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration.	3DIC	2009	DBLP DOI BibTeX RDF
47	DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De	Analytical Model for the Propagation Delay of Through Silicon Vias.	ISQED	2008	DBLP DOI BibTeX RDF	3D integrated circuits, propagation delay model, dimensional analysis, TSV
47	Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller	Design and CAD for 3D integrated circuits.	DAC	2008	DBLP DOI BibTeX RDF	thermal modeling, TSV, through silicon via, 3DIC
40	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
40	Xiang Zhang, Hongda Li, Yuzhong Qu	Finding Important Vocabulary Within Ontology.	ASWC	2006	DBLP DOI BibTeX RDF
36	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
32	Jinhyung Lee, Kyungjun Cho, Chang Kwon Lee, Yeonho Lee 0002, Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Chang-Ki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim	13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization.	ISSCC	2024	DBLP DOI BibTeX RDF
32	Kangkang Xu, Yang Yu 0015, Xiyuan Peng	TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test.	VTS	2021	DBLP DOI BibTeX RDF
32	Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran	TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
32	Tianming Ni, Yao Yao, Hao Chang, Lin Lu, Huaguo Liang, Aibin Yan, Zhengfeng Huang, Xiaoqing Wen	LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
32	Tanusree Kaibartta, G. P. Biswas, Debesh Kumar Das	Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs.	J. Electron. Test.	2020	DBLP DOI BibTeX RDF
32	Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran	TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects.	ISVLSI	2019	DBLP DOI BibTeX RDF
32	Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed	A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors.	ITC-Asia	2019	DBLP DOI BibTeX RDF
32	Jaeseok Park, Minho Cheong, Sungho Kang	R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies.	IEEE Trans. Reliab.	2017	DBLP DOI BibTeX RDF
32	Saikat Mondal, Sang-Bock Cho, Bruce C. Kim	Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
32	Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman 0001, Chandan Giri	TSV repairing for 3D ICs using redundant TSV.	ISED	2017	DBLP DOI BibTeX RDF
32	Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi, Nader Bagherzadeh, Michael M. Green	Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
32	Yarui Peng, Dusan Petranovic, Sung Kyu Lim	Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
32	Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi, Nader Bagherzadeh	Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC.	NOCS	2015	DBLP DOI BibTeX RDF
32	Joke De Messemaeker, O. Varela Pedreira, A. Moussa, Nabi Nabiollahi, Kris Vanstreels, Stefaan Van Huylenbroeck, Harold Philipsen, Patrick Verdonck, Bart Vandevelde, Ingrid De Wolf, Eric Beyne, Kris Croes	Impact of oxide liner properties on TSV Cu pumping and TSV stress.	IRPS	2015	DBLP DOI BibTeX RDF
32	Quan Deng, Minxuan Zhang, Zhenyu Zhao, Peng Li	Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC.	NCCET	2015	DBLP DOI BibTeX RDF
32	Caleb Serafy, Bing Shi, Ankur Srivastava 0001	A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.	Integr.	2014	DBLP DOI BibTeX RDF
32	Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim	Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
32	Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang	Fault-tolerant TSV by using scan-chain test TSV.	ASP-DAC	2014	DBLP DOI BibTeX RDF
32	Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh	TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip.	DFT	2014	DBLP DOI BibTeX RDF
32	Khaled Salah 0001	Performance comparison between air-gap based coaxial TSV and conventional circular TSV in 3D-ICs.	IDT	2013	DBLP DOI BibTeX RDF
32	Zao Liu, Sahana Swarup, Sheldon X.-D. Tan	Compact lateral thermal resistance modeling and characterization for TSV and TSV array.	ICCAD	2013	DBLP DOI BibTeX RDF
32	Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim	On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs.	ICCAD	2013	DBLP DOI BibTeX RDF
32	Byunghyun Lee, Taewhan Kim	High-level TSV resource sharing and optimization for TSV based 3D IC designs.	SoCC	2013	DBLP DOI BibTeX RDF
32	Caleb Serafy, Bing Shi, Ankur Srivastava 0001	Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
32	Shu-Han Wei, Yu-Min Lee, Chia-Tung Ho, Chih-Ting Sun, Liang-Chia Cheng	Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.	VLSI-DAT	2013	DBLP DOI BibTeX RDF
32	Taigon Song, Chang Liu 0034, Yarui Peng, Sung Kyu Lim	Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs.	DAC	2013	DBLP DOI BibTeX RDF
32	Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin	Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix.	ISQED	2012	DBLP DOI BibTeX RDF
32	Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang	TSV sharing through multiplexing for TSV count minimization in high-level synthesis.	SoCC	2011	DBLP DOI BibTeX RDF
32	Taigon Song, Chang Liu 0034, Dae Hyun Kim 0004, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon	Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.	ISQED	2011	DBLP DOI BibTeX RDF
32	Chang Liu 0034, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim	Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC.	DAC	2011	DBLP DOI BibTeX RDF
27	Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu	DfT Architecture for 3D-SICs with Multiple Towers.	ETS	2011	DBLP DOI BibTeX RDF	three-dimensional stacking, 3D-SIC, multi-tower, DfT, wrapper, design-for-test, TSV, through-silicon via
27	Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon	Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study.	DAC	2009	DBLP DOI BibTeX RDF	FFT, SAR, TSV, 3DIC
20	Hsiu-Ming Chang 0001, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu	An error tolerance scheme for 3D CMOS imagers.	DAC	2010	DBLP DOI BibTeX RDF	image sensor, error tolerance, 3D IC
20	Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic	3-D stacked die: now or future?	DAC	2010	DBLP DOI BibTeX RDF	integrated circuits, 3-D
20	Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka	Three-dimensional integration technology and integrated systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
20	Nobuaki Miyakawa	A 3D prototyping chip based on a wafer-level stacking technology.	ASP-DAC	2009	DBLP DOI BibTeX RDF
20	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
20	Cesare Ferri, Sherief Reda, R. Iris Bahar	Parametric yield management for 3D ICs: Models and strategies for improvement.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance, process variations, leakage, 3D integration, yield management
20	Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda	Multilayer stacking technology using wafer-to-wafer stacked method.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	stacking process, design, hardware, 3D integration
20	Cesare Ferri, Sherief Reda, R. Iris Bahar	Strategies for improving the parametric yield and profits of 3D ICs.	ICCAD	2007	DBLP DOI BibTeX RDF
16	Chen Wei, Xiaole Cui, Xiaoxin Cui	Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays.	IEEE Trans. Reliab.	2024	DBLP DOI BibTeX RDF
16	Jun Liu 0070, Songren Cheng, Tian Chen, Xi Wu 0003, Huaguo Liang	A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Yanan Tao, Chao Liang, Ziqi Mei, Zhiqiang Song, Yu Wu, Yunna Sun, Wenqiang Zhang, Yong Ruan, Xiaoguang Zhao	Numerical simulation of copper electrodeposition for Through Silicon Via (TSV) with SPS-PEG-Cl additive system.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Jilin Kou, Xiangkun Yin, Jiangfan Liu, Kai Jing, Ningmei Yu, Yuan Yang 0006, Qian Li	A compact fifth-order SIW BPF based on TSV technology with high selectivity.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
16	Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee 0002, Jieun Jang, Joohwan Cho	A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
16	Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung	An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
16	Jindong Zhou, Yuyang Chen, Youliang Jing, Pingqiang Zhou	The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs.	Integr.	2023	DBLP DOI BibTeX RDF
16	Peng Xu, Huan Huang, Bing-Qi Zhang, Zheng-Hua Tang	Thermal Performance Analysis of Carbon Materials Based TSV in Three Dimensional Integrated Circuits.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Huangyin Wang, Yikai Xiong, Liming Geng	Modeling and Thermal Stress Coupling Optimization Design of TSV Inductors in On-Chip DC/DC Converters.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang	ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Youngkwang Lee, Donghyun Han, Sungho Kang 0001	TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Yang Ge, Tejinder Singh Sandhu, Dmitri V. Truhachev, Kamal El-Sankary	A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Wenbo Guan, Xiaoyan Tang, Hongliang Lu, Yuming Zhang, Yimen Zhang	A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Xianglong Wang, Dongdong Chen 0010, Di Li 0003, Chen Kou, Yintang Yang	The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System.	Symmetry	2023	DBLP DOI BibTeX RDF
16	Xianglong Wang, Yintang Yang, Dongdong Chen 0010, Di Li 0003	A High-Efficiency Design Method of TSV Array for Thermal Management of 3-D Integrated System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui	Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Tao Gong, Si Chen, Kai Li, Guoyuan Li, Zhizhe Wang, Xiaofeng Yang, Xiaodong Jian, Zhiwei Fu	Study on the electrical breakdown failure mode transition of TSV-RDL.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Zhuoyu Yang, Xiangkun Yin, Ningmei Yu, Yuan Yang	TSV-based SIW bandpass filter with adjustable transmission zeros for D-band applications.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
16	Tsague Cathy, Medjo Astrid, Jean Seutche, Tchinda Rene	Assessment of Thermal Comfort Using PMV, aPMV, ePMV and TSV Indices in a Naturally Ventilated Building.	SAFER-TEA	2023	DBLP DOI BibTeX RDF
16	Jiayi Shen, Chang Liu, Tadaaki Hoshi, Atsushi Sinoda, Hisashi Kino, Tetsu Tanaka, Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima	Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last.	3DIC	2023	DBLP DOI BibTeX RDF
16	Song Wang, Bing Yu, Wenwu Xiao, Fujun Bai, Xiaodong Long, Liang Bai, Xuerong Jia, Fengguo Zuo, Jie Tan, Yixin Guo, Peng Sun, Jun Zhou, Qiong Zhan, Sheng Hu, Yu Zhou, Yi Kang, Qiwei Ren, Xiping Jiang	A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
16	C.-L. Lu, C.-H. Chuang, C.-H. Huang, S.-C. Lin, Y.-H. Chang, W.-Y. Lai, M.-H. Chiu, Ming Han Liao, S.-Z. Chang	4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
16	Taeryeong Kim, Ji-Young Kim, Jeonghyeok You, Hohyun Chae, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung	A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
16	Takeshi Ohkawa, Masahiro Aoyagi	FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
16	He Junsen, Dong-Hyun Yoon, Tony Tae-Hyoung Kim	An Effective Faulty TSV Detection Scheme for TSVs in High Bandwidth Memory.	ISCAS	2023	DBLP DOI BibTeX RDF
16	Sunghoon Kim, Donghyun Han, Seokjun Jang, Sungho Kang 0001	LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture.	ISOCC	2023	DBLP DOI BibTeX RDF
16	Junpeng Wang, Christoph Neuhauser, Jun Wu 0005, Xifeng Gao, Rüdiger Westermann	3D-TSV: The 3D trajectory-based stress visualizer.	Adv. Eng. Softw.	2022	DBLP DOI BibTeX RDF
16	Yingbo Zhao, Qingyang Fan	Frequency-Dependent Characteristics and Parametric Modeling of the Silicon Substrate in TSV-Based 3-D ICs.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Xiangliang Li, Peng Zhao 0003, Shichang Chen, Kuiwen Xu, Gaofeng Wang	A Deep-Learning Approach for Wideband Design of 3D TSV-Based Inductors.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Kai Zhang, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006	A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
16	Qi Xu, Hao Geng, Tianming Ni, Song Chen 0001, Bei Yu 0001, Yi Kang, Xiaoqing Wen	Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Sangmin Park, Minho Cheong, Donghyun Han, Sungho Kang 0001	Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Qi Xu, Wenhao Sun, Song Chen 0001, Yi Kang, Xiaoqing Wen	Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Kangkang Xu, Yang Yu 0015, Xu Fang	The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
16	Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri	A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs.	ACM J. Emerg. Technol. Comput. Syst.	2022	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Ruiqi Li, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006	Compact high-performance dual-frequency power divider based on TSV.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
16	Chenyi Wen, Xiao Dong, Baixin Chen, Umamaheswara Rao Tida, Yiyu Shi 0001, Cheng Zhuo	Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter.	ACM Trans. Design Autom. Electr. Syst.	2022	DBLP DOI BibTeX RDF
16	Shashikiran Venkatesha, Ranjani Parthasarathi	A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems.	CoRR	2022	DBLP DOI BibTeX RDF
16	Chen Wei, Xiaole Cui, Xiaoxin Cui	A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
16	Tianming Ni, Jingchang Bian, Zhao Yang, Mu Nie, Liang Yao, Zhengfeng Huang, Aibin Yan, Xiaoqing Wen	Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement.	IEEE Des. Test	2022	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Sa Xiao, Xiangkun Yin, Ningmei Yu, Yuan Yang 0006	A miniature TSV-based branch line coupler using π equivalent circuit model for transmission line.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
16	Fengjuan Wang, Quan Peng, Ningmei Yu, Yuan Yang	TSV-based SIW bandpass filter for W-band mobile communication applications.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
16	Yuchen Wu, Yao Liu, Zhao Zhao, Chunfeng Liu 0001, Wenyu Qu	TSV-MAC: Time Slot Variable MAC Protocol Based on Deep Reinforcement Learning for UASNs.	WASA (3)	2022	DBLP DOI BibTeX RDF
16	H. Zheng, Y. S. Sun, J. L. Huang	Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking.	IRPS	2022	DBLP DOI BibTeX RDF