Search results for "TriMedia"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
151	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
117	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	IEEE-Compliant IDCT on FPGA-Augmented TriMedia.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor
117	Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven	Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.	ASAP	2003	DBLP DOI BibTeX RDF
100	Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	Pel reconstruction on FPGA-augmented TriMedia.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
82	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.	FCCM	2002	DBLP DOI BibTeX RDF
78	A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans	TriMedia CPU64 Application Domain and Benchmark Suite.	ICCD	1999	DBLP DOI BibTeX RDF	TriMedia, multi-media benchmark, design space exploration, embedded processors, VLIW processors, media processing
65	Harald P. E. Vranken	Debug Facilities in the TriMedia CPU64 Architecture.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	application debug, VLIW processor, design-for-debug
48	Norbert Esser, Renga Sundararajan, Joachim Trescher	Improving TriMedia Cache Performance by Profile Guided Code Reordering.	SAMOS	2007	DBLP DOI BibTeX RDF	cache, profiling, code layout
48	Frans Sijstermans	The TriMedia processor: the price-performance challenge for media processing.	ICME	2001	DBLP DOI BibTeX RDF
48	Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans	TriMedia CPU64 Design Space Exploration.	ICCD	1999	DBLP DOI BibTeX RDF
48	Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt	TriMedia CPU64 Application Development Environment.	ICCD	1999	DBLP DOI BibTeX RDF
48	Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel	TriMedia CPU64 Architecture.	ICCD	1999	DBLP DOI BibTeX RDF
35	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
31	Juan Carlos Rojas, Miriam Leeser	Programming portable optimized multimedia applications.	ACM Multimedia	2003	DBLP DOI BibTeX RDF	TriMedia, optimization, multimedia, SIMD, portability, MMX, SSE, AltiVec, SSE2
31	Thomas McGee, Lalitha Agnihotri, Nevenka Dimitrova	Transcript Triggers for Digital TV.	ICME	2001	DBLP DOI BibTeX RDF	Content Augmentation, TriMedia, Digital Television, Closed Caption
30	Oliver Schreer, Michael Karl 0001, Peter Kauff	A TriMedia based multi-processor system using PCI technology for immersive videoconference terminals.	DSP	2002	DBLP DOI BibTeX RDF
30	Miguel Miranda, C. Ghez, Erik Brockmeyer, Pieter Op de Beeck, Francky Catthoor	Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor.	SBCCI	2002	DBLP BibTeX RDF
30	Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers	An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.	FCCM	2001	DBLP DOI BibTeX RDF
30	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.	ICCD	2001	DBLP DOI BibTeX RDF
30	Jan Hoogerbrugge, Lex Augusteijn	Instruction Scheduling for TriMedia.	J. Instr. Level Parallelism	1999	DBLP BibTeX RDF
30	Harald P. E. Vranken	Debug facilities in the TriMedia CPU64 architecture.	ETW	1999	DBLP DOI BibTeX RDF
30	Joseph Sgro	A High Bandwidth Scalable Multiprocessor System Based on the TriMedia TM1XOO.	PDPTA	1999	DBLP BibTeX RDF
30	Frans Sijstermans, Evert-Jan D. Pol, Bram Riemens, Kees A. Vissers, Selliah Rathnam, Gert Slavenburg	Design space exploration for future TriMedia CPUs.	ICASSP	1998	DBLP DOI BibTeX RDF
17	Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven	Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Predictability, Multiprocessor, Compositionality, Cache management
17	Dominic A. Antonelli, Alan Jay Smith, Jan-Willem van de Waerdt	Power consumption and reduction in a real, commercial multimedia core.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	tm3270, multimedia, power, energy, compiler optimization, cache memory, embedded processor
17	Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurlink, Andrei Sergeevich Terechko, Jan Hoogerbrugge, Mauricio Alvarez 0001, Alex Ramírez	Parallel H.264 Decoding on an Embedded Multicore Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
17	Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana	Compositional, dynamic cache management for embedded chip multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
17	Andrei Sergeevich Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
17	Simone Boragno, Boghos A. Boghossian, James Black, Dimitrios Makris 0001, Sergio A. Velastin	A DSP-based system for the detection of vehicles parked in prohibited areas.	AVSS	2007	DBLP DOI BibTeX RDF
17	Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren 0001	Retargetable code optimization with SIMD instructions.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	SIMD, vectorization, subword parallelism, retargetable compilers
17	Jason C. Chen, Chun-Fu Shen, Shao-Yi Chien	CRISP: coarse-grain reconfigurable image signal processor for digital still cameras.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Björn Franke, Michael F. P. O'Boyle, John Thomson, Grigori Fursin	Probabilistic source-level optimisation of embedded programs.	LCTES	2005	DBLP DOI BibTeX RDF	source-level optimization, digital signal processing, iterative compilation, adaptive compilation, feedback-directed optimization
17	Jan-Willem van de Waerdt, Gerrit A. Slavenburg, Jean-Paul van Itegem, Stamatis Vassiliadis	Motion estimation performance of the TM3270 processor.	SAC	2005	DBLP DOI BibTeX RDF	motion estimation, software implementation, media processor
17	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen	The TM3270 Media-Processor.	MICRO	2005	DBLP DOI BibTeX RDF
17	Daniel Kästner, Markus Pister 0002	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
17	Jan-Willem van de Waerdt, Stamatis Vassiliadis	Instruction Set Architecture Enhancements for Video Processing.	ASAP	2005	DBLP DOI BibTeX RDF
17	Bang Jun Lei, C. Chang, Emile A. Hendriks	An efficient image-based telepresence system for videoconferencing.	IEEE Trans. Circuits Syst. Video Technol.	2004	DBLP DOI BibTeX RDF
17	Björn Franke, Michael F. P. O'Boyle	Array recovery and high-level transformations for DSP applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Pointer conversion, high-level transformations, embedded processors, dataflow graphs
17	Pieter Op de Beeck, C. Ghez, Erik Brockmeyer, Miguel Miranda, Francky Catthoor, Geert Deconinck	Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.	DATE	2003	DBLP DOI BibTeX RDF
17	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Exploring Storage Organization in ASIP Synthesis.	DSD	2003	DBLP DOI BibTeX RDF
17	Björn Decker 0002, Daniel Kästner	Reconstructing Control Flow from Predicated Assembly Code.	SCOPES	2003	DBLP DOI BibTeX RDF
17	Daniel Kästner	TDL: A Hardware Description Language for Retargetable Postpass Optimizations and Analyses.	GPCE	2003	DBLP DOI BibTeX RDF
17	Daniel Kästner, Stephan Wilhelm	Generic control flow reconstruction from assembly code.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	control flow reconstruction, embedded processors, call graph, retargetable compilers, assembly code, postpass optimization
17	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
17	Manvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, Srinivasan Balakrishnan	Speculative Trace Scheduling in VLIW Processors.	ICCD	2002	DBLP DOI BibTeX RDF
17	Sidney Cadot, Frits Kuijlman, Koen Langendoen, Kees van Reeuwijk, Henk J. Sips	ENSEMBLE: A Communication Layer for Embedded Multi-Processor Systems.	LCTES/OM	2001	DBLP DOI BibTeX RDF
17	Björn Franke, Michael F. P. O'Boyle	An empirical evaluation of high level transformations for embedded processors.	CASES	2001	DBLP DOI BibTeX RDF
17	Craig S. K. Clapp	Joint Hardware / Software Design of a Fast Stream Cipher.	FSE	1998	DBLP DOI BibTeX RDF
17	Bas Aarts, Michel Barreteau, François Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, André Seznec, Elena Stöhr, Marco Verhoeven, Harry A. G. Wijshoff	OCEANS: Optimizing Compilers for Embedded Applications.	Euro-Par	1997	DBLP DOI BibTeX RDF