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Publication years (Num. hits)
1988-1992 (15) 1993-1996 (18) 1998-2000 (17) 2001-2003 (19) 2004-2005 (17) 2006-2010 (16) 2012-2021 (7)
Publication types (Num. hits)
article(44) book(1) inproceedings(63) phdthesis(1)
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Found 109 publication records. Showing 109 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
89Seung-Min Lee, Stefan Lachowicz, David Lucas, A. M. Rassau, Kamran Eshraghian, Mike Myung-Ok Lee, Kamal E. Alameh A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
73M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
67Stephan P. Athan, David L. Landis, Sami A. Al-Arian A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
67Imtiaz P. Shaik, Michael L. Bushnell A graph approach to DFT hardware placement for robust delay fault BIST. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
67Payam Heydari, Massoud Pedram Interconnect Energy Dissipation in High-Speed ULSI Circuits. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines
64Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57Seung-Min Lee, David Lucas, Mike Myung-Ok Lee, Kamran Eshraghian, Dae-Ik Kim, Kamal E. Alameh High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS. Search on Bibsonomy HSNMC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
57Yi-Kan Cheng, Sung-Mo Kang Temperature-driven power and timing analysis for CMOS ULSI circuits. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
51Eiji Harada, Janak H. Patel Overhead reduction techniques for hierarchical fault simulation. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
48Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan The physical design of on-chip interconnections. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
42Bogdan M. Maziarz, Vijay K. Jain Automatic Reconfiguration and Yield of the TESH Multicomputer Network. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF TESH, fault-tolerance, routing, VLSI, Interconnection networks, reconfiguration, redundancy, yield, hierarchical networks, manufacturing defects, parallel computing systems, ULSI
41Ron Ho High-performance ULSI: the real limiter to interconnect scaling. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF VLSI, wireless, 3D, scaling, proximity, repeaters, wires
41Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
41Pasi Liljeberg, Juha Plosila, Jouni Isoaho Asynchronous interface for locally clocked modules in ULSI systems. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
41Yi-Kan Cheng, Sung-Mo Kang A temperature-aware simulation environment for reliable ULSI chipdesign. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
41Yi-Kan Cheng, Sung-Mo Kang An efficient method for hot-spot identification in ULSI circuits. Search on Bibsonomy ICCAD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
41Daniel Audet, Yvon Savaria, N. Arel Pipelining communications in large VLSI/ULSI systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
41Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
41Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura A ULSI 2-D capacitance simulator for complex structures based on actual processes. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
41Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen Three-dimensional capacitance computations for VLSI/ULSI interconnections. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
32Baohua Wang, Pinaki Mazumder Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Assessment of on-chip wire-length distribution models. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Yves Quéré, Thierry LeGouguec, Pierre-Marie Martin, Fabrice Huret Interconnect Mode Conversion in High-Speed VLSI Circuits. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Kevin T. Tang, Eby G. Friedman Simultaneous switching noise in on-chip CMOS power distribution networks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Bogdan M. Maziarz, Vijay K. Jain Yield Estimates for the TESH Multicomputer Network. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Hannu Tenhunen, Elena Dubrova SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. Search on Bibsonomy MSE The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
26Tobias Bjerregaard, Shankar Mahadevan A survey of research and practices of Network-on-chip. Search on Bibsonomy ACM Comput. Surv. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
25George Mekhael, Nathaniel Morgan, Mounica Patnala, Trond Ytterdal, Maher E. Rizkalla GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. Search on Bibsonomy ISCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
25Ajay Kumar 0004, Neha Gupta 0003, Samarth Singh, Balark Tiwari, Madan Mohan Tripathi, Rishu Chaujar Carbon Nanotube Recessed Channel (CNT-RC) MOSFET for High Linearity/ULSI Applications. Search on Bibsonomy TENCON The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
25Michihiro Sato, Yosuke Takahashi Simulation of Dislocation Accumulation in Impurity Doped-ULSI Cells and Electric Characteristic Evaluations. Search on Bibsonomy Int. J. Autom. Technol. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
25Pascal Nsame, Guy Bois, Yvon Savaria A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. Search on Bibsonomy ICECS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide. Search on Bibsonomy ASICON The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
25Cher Ming Tan, Wei Li, Zhenghao Gan Applications of finite element methods for reliability study of ULSI interconnections. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
25Carles Hernández 0001, Federico Silla, José Duato Addressing Link Degradation in NoC-Based ULSI Designs. Search on Bibsonomy Euro-Par Workshops The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
25Cher Ming Tan Electromigration in ULSI Interconnections Search on Bibsonomy 2010   DOI  RDF
25Tong Boon Tang, Alan F. Murray, Binjie Cheng, Asen Asenov Statistical NBTI-effect prediction for ULSI circuits. Search on Bibsonomy ISCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
25Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. Search on Bibsonomy Microelectron. J. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Md. Sajjad Rahaman, Masud H. Chowdhury Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. Search on Bibsonomy ICECS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Xia Xiao, Xueyi You, Suying Yao Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method. Search on Bibsonomy Microelectron. J. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Jae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang, Tim P. Butler, David G. Hasko, Jong Min Kim, Gehan A. J. Amaratunga CNT based mechanical devices for ULSI memory. Search on Bibsonomy CICC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Amir H. Ajami, Kaustav Banerjee, Massoud Pedram Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25M. Frank Chang CDMA/FDMA-interconnects for future ULSI communications. Search on Bibsonomy ICCAD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Payam Heydari, Soroush Abbaspour, Massoud Pedram Interconnect energy dissipation in high-speed ULSI circuits. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu ULSI Interconnect Length Distribution Model Considering Core Utilization. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Michael W. Ruprecht, Guenther Benstetter, Douglas B. Hunt A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
25Ulrich Rückert 0001 ULSI Architectures for Artificial Neural Networks. Search on Bibsonomy IEEE Micro The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Guenther Benstetter, Michael W. Ruprecht, Douglas B. Hunt A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Shuzhou Fang, Zeyi Wang, Xianlong Hong A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Yutao Ma, Zhijian Li, Litian Liu New strategy of modeling inversion layer characteristics in MOS structure for ULSI applications. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Ulrich Rückert 0001 ULSI Architectures for Artificial Neural Networks. Search on Bibsonomy PDP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25TingYen Chiang, Kaustav Banerjee, Krishna Saraswat Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. Search on Bibsonomy ICCAD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Kaustav Banerjee, Amit Mehrotra Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. Search on Bibsonomy ICCAD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Andreas Hieke A Monte Carlo / FEM investigation on optimal cross-section of high speed ULSI interconnects with respect to RC-delay. Search on Bibsonomy CATA The full citation details ... 2000 DBLP  BibTeX  RDF
25Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen Combating digital noise in high speed ULSI circuits using binary BCH encoding. Search on Bibsonomy ISCAS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong Coupling Noise Analysis for VLIS and ULSI Circuits. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Crosstalk Analysis, Crosstalk Modeling, Noise
25Michael Armacost, Peter D. Hoh, Richard Wise, Wendy Yan, Jeffrey J. Brown, John H. Keller, George A. Kaplita, Scott D. Halle, K. Paul Muller, Munir D. Naeem, Senthil Srinivasan, Hung Y. Ng, Martin Gutsche, Alois Gutmann, Bruno Spuler Plasma-etching processes for ULSI semiconductor circuits. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Donna R. Cote, Son Van Nguyen, Anthony K. Stamper, Douglas S. Armbrust, Dirk Tobben, Richard A. Conti, Gill Yong Lee Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits. Search on Bibsonomy IBM J. Res. Dev. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25D. Stroobannt PIN count prediction in ratio cut partitioning for VLSI and ULSI. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Eliane França Projeto de um circuito integrado dedicado a simulação de circuitos ULSI. Search on Bibsonomy 1999   RDF
25Hoan H. Pham, Arokia Nathan A new formulation for accurate numerical extraction of interconnect capacitance in ULSI. Search on Bibsonomy ICECS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
25Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
25Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango Standby/active mode logic for sub-1-V operating ULSI memory. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
25R. Kent Smith, William M. Coughran Jr. Computational Challenges in Simulations of ULSI Semiconductor Devices. Search on Bibsonomy HICSS (1) The full citation details ... 1994 DBLP  BibTeX  RDF
25S. K. Lahiri 0001, M. K. Das, A. Das Gupta, I. Manna 3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. Search on Bibsonomy VLSI Design The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
25Yoshiharu Ichikawa, Jun-ichiro Toriwaki A Digital ULSI Inspection Method Using Parallel Scanning Confocal Microscope. Search on Bibsonomy MVA The full citation details ... 1994 DBLP  BibTeX  RDF
25Tadahiro Ohmi ULSI reliability through ultraclean processing. Search on Bibsonomy Proc. IEEE The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
25Mohamed Nekili, Yvon Savaria Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. Search on Bibsonomy ISCAS The full citation details ... 1993 DBLP  BibTeX  RDF
25Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. Search on Bibsonomy ICCD The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. Search on Bibsonomy ITC The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
25Nobuhiro Tomabechi A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems. Search on Bibsonomy Syst. Comput. Jpn. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
25Moshe Shahaf DesignFab: A Methodology for ULSI Microprocessor Design. Search on Bibsonomy ICCD The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
25Gopi Ganapathy, Jacob A. Abraham Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. Search on Bibsonomy ITC The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
25A. Reisman Ionizing radiation effects on ULSI device yield and reliability. Search on Bibsonomy J. Supercomput. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
25Sandro Solmi, Renato Angelucci, Marco Merli Shallow junctions for ULSI technology. Search on Bibsonomy Eur. Trans. Telecommun. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
25Arnaldo Hilário Viegas de Lima, Raul César B. Martins, Ronaldo Stern, Luiza Maria F. Carneiro GARDEN - An Integrated and Evolving Environment for ULSI/VLSI CAD Applications. Search on Bibsonomy IBM Syst. J. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
25F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin NOISY: an electrical noise checker for ULSI. Search on Bibsonomy ICCAD The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
16Md. Sajjad Rahaman, Masud H. Chowdhury BER performance comparison between CDMA and UWB for RF/wireless interconnect application. Search on Bibsonomy EIT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira Efficient Representation and Analysis of Power Grids. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16Saurabh Jain, W. Robert Daasch, David Armbrust Analyzing the Impact of Fault Tolerant BIST for VLSI Design. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
16Ray T. Chen Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF PCB interconnects, optical bus architecture, optical interconnects
16Yiyu Shi 0001, Lei He 0001 Empire: an efficient and compact multiple-parameterized model order reduction method. Search on Bibsonomy ISPD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF reduction, sensitivity, parameter
16Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl IntSim: A CAD tool for optimization of multilevel interconnect networks. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
16Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Impact of interconnect length changes on effective materials properties (dielectric constant). Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance, routing, interconnect, cycle time, interconnect model, rent, path delay
16Zhe Feng 0002, Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF ?-geometry, O(nlogn), Steiner tree construction, obstacle-avoiding
16Qi Zhu 0002, Hai Zhou 0001, Tong Jing, Xianlong Hong, Yang Yang 0040 Spanning graph-based nonrectilinear steiner tree algorithms. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Yu Hu 0002, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu 0001, Guiying Yan An-OARSMan: obstacle-avoiding routing tree construction with good length performance. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan The polygonal contraction heuristic for rectilinear Steiner tree construction. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Yaw-Jen Chang Fault Detection for Plasma Etching Processes Using RBF Neural Networks. Search on Bibsonomy ISNN (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
16Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. Search on Bibsonomy SLIP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF wire-length distribution model, routing, interconnect, rent
16Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation
16Joohyung Lee 0004, Yogesh B. Gianchandani A scanning thermal microscopy system with a temperature dithering, servo-controlled interface circuit. Search on Bibsonomy ISCAS (4) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
16Vijay K. Jain, Glenn H. Chapman Level-Hybrid Optoelectronic TESH Interconnection Network. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
16Abhisek Dixit, V. Ramgopal Rao A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. Search on Bibsonomy VLSI Design The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
16Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier Few electron devices: towards hybrid CMOS-SET integrated circuits. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics
16Gerard A. Allan Yield prediction by sampling IC layout. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
16Yi-Kan Cheng, David Bearden, Kanti Suryadevara Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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