Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
89 | Seung-Min Lee, Stefan Lachowicz, David Lucas, A. M. Rassau, Kamran Eshraghian, Mike Myung-Ok Lee, Kamal E. Alameh |
A Novel Design of Beam Steering n-phase OPTO-ULSI Processor for IIPS. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
73 | M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi |
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
67 | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices |
67 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
67 | Payam Heydari, Massoud Pedram |
Interconnect Energy Dissipation in High-Speed ULSI Circuits. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Ultra-large integrated (ULSI) circuits, Energy dissipation CMOS circuits, RLC circuits, Interconnect, Transmission lines |
64 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Seung-Min Lee, David Lucas, Mike Myung-Ok Lee, Kamran Eshraghian, Dae-Ik Kim, Kamal E. Alameh |
High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS. |
HSNMC |
2004 |
DBLP DOI BibTeX RDF |
|
57 | Yi-Kan Cheng, Sung-Mo Kang |
Temperature-driven power and timing analysis for CMOS ULSI circuits. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Eiji Harada, Janak H. Patel |
Overhead reduction techniques for hierarchical fault simulation. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI |
48 | Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan |
The physical design of on-chip interconnections. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
42 | Bogdan M. Maziarz, Vijay K. Jain |
Automatic Reconfiguration and Yield of the TESH Multicomputer Network. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
TESH, fault-tolerance, routing, VLSI, Interconnection networks, reconfiguration, redundancy, yield, hierarchical networks, manufacturing defects, parallel computing systems, ULSI |
41 | Ron Ho |
High-performance ULSI: the real limiter to interconnect scaling. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
VLSI, wireless, 3D, scaling, proximity, repeaters, wires |
41 | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan |
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Pasi Liljeberg, Juha Plosila, Jouni Isoaho |
Asynchronous interface for locally clocked modules in ULSI systems. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Yi-Kan Cheng, Sung-Mo Kang |
A temperature-aware simulation environment for reliable ULSI chipdesign. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Yi-Kan Cheng, Sung-Mo Kang |
An efficient method for hot-spot identification in ULSI circuits. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Daniel Audet, Yvon Savaria, N. Arel |
Pipelining communications in large VLSI/ULSI systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
41 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima |
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. |
IEEE Des. Test Comput. |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura |
A ULSI 2-D capacitance simulator for complex structures based on actual processes. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
41 | Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen |
Three-dimensional capacitance computations for VLSI/ULSI interconnections. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
32 | Baohua Wang, Pinaki Mazumder |
Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Assessment of on-chip wire-length distribution models. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Yves Quéré, Thierry LeGouguec, Pierre-Marie Martin, Fabrice Huret |
Interconnect Mode Conversion in High-Speed VLSI Circuits. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Kevin T. Tang, Eby G. Friedman |
Simultaneous switching noise in on-chip CMOS power distribution networks. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Bogdan M. Maziarz, Vijay K. Jain |
Yield Estimates for the TESH Multicomputer Network. |
DFT |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Hannu Tenhunen, Elena Dubrova |
SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. |
MSE |
2001 |
DBLP DOI BibTeX RDF |
|
32 | R. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla |
Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
26 | Tobias Bjerregaard, Shankar Mahadevan |
A survey of research and practices of Network-on-chip. |
ACM Comput. Surv. |
2006 |
DBLP DOI BibTeX RDF |
Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions |
25 | George Mekhael, Nathaniel Morgan, Mounica Patnala, Trond Ytterdal, Maher E. Rizkalla |
GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Ajay Kumar 0004, Neha Gupta 0003, Samarth Singh, Balark Tiwari, Madan Mohan Tripathi, Rishu Chaujar |
Carbon Nanotube Recessed Channel (CNT-RC) MOSFET for High Linearity/ULSI Applications. |
TENCON |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Michihiro Sato, Yosuke Takahashi |
Simulation of Dislocation Accumulation in Impurity Doped-ULSI Cells and Electric Characteristic Evaluations. |
Int. J. Autom. Technol. |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Pascal Nsame, Guy Bois, Yvon Savaria |
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. |
ICECS |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang |
PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide. |
ASICON |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Cher Ming Tan, Wei Li, Zhenghao Gan |
Applications of finite element methods for reliability study of ULSI interconnections. |
Microelectron. Reliab. |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Carles Hernández 0001, Federico Silla, José Duato |
Addressing Link Degradation in NoC-Based ULSI Designs. |
Euro-Par Workshops |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Cher Ming Tan |
Electromigration in ULSI Interconnections |
|
2010 |
DOI RDF |
|
25 | Tong Boon Tang, Alan F. Murray, Binjie Cheng, Asen Asenov |
Statistical NBTI-effect prediction for ULSI circuits. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho |
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. |
Microelectron. J. |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. |
ICECS |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Xia Xiao, Xueyi You, Suying Yao |
Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method. |
Microelectron. J. |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Jae Eun Jang, Seung Nam Cha, Youngjin Choi, Dae Joon Kang, Tim P. Butler, David G. Hasko, Jong Min Kim, Gehan A. J. Amaratunga |
CNT based mechanical devices for ULSI memory. |
CICC |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Amir H. Ajami, Kaustav Banerjee, Massoud Pedram |
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
25 | M. Frank Chang |
CDMA/FDMA-interconnects for future ULSI communications. |
ICCAD |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Payam Heydari, Soroush Abbaspour, Massoud Pedram |
Interconnect energy dissipation in high-speed ULSI circuits. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu |
ULSI Interconnect Length Distribution Model Considering Core Utilization. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Michael W. Ruprecht, Guenther Benstetter, Douglas B. Hunt |
A review of ULSI failure analysis techniques for DRAMs. Part II: Defect isolation and visualization. |
Microelectron. Reliab. |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Ulrich Rückert 0001 |
ULSI Architectures for Artificial Neural Networks. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Guenther Benstetter, Michael W. Ruprecht, Douglas B. Hunt |
A review of ULSI failure analysis techniques for DRAMs 1. Defect localization and verification. |
Microelectron. Reliab. |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Shuzhou Fang, Zeyi Wang, Xianlong Hong |
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Yutao Ma, Zhijian Li, Litian Liu |
New strategy of modeling inversion layer characteristics in MOS structure for ULSI applications. |
Sci. China Ser. F Inf. Sci. |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Ulrich Rückert 0001 |
ULSI Architectures for Artificial Neural Networks. |
PDP |
2001 |
DBLP DOI BibTeX RDF |
|
25 | TingYen Chiang, Kaustav Banerjee, Krishna Saraswat |
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. |
ICCAD |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Kaustav Banerjee, Amit Mehrotra |
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. |
ICCAD |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung |
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Andreas Hieke |
A Monte Carlo / FEM investigation on optimal cross-section of high speed ULSI interconnects with respect to RC-delay. |
CATA |
2000 |
DBLP BibTeX RDF |
|
25 | Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Combating digital noise in high speed ULSI circuits using binary BCH encoding. |
ISCAS |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Kathirgamar Aingaran, Fabian Klass, Chin-Man Kim, Chaim Amir, Joydeep Mitra, Eileen You, Jamil Mohd, Sai-keung Dong |
Coupling Noise Analysis for VLIS and ULSI Circuits. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Crosstalk Analysis, Crosstalk Modeling, Noise |
25 | Michael Armacost, Peter D. Hoh, Richard Wise, Wendy Yan, Jeffrey J. Brown, John H. Keller, George A. Kaplita, Scott D. Halle, K. Paul Muller, Munir D. Naeem, Senthil Srinivasan, Hung Y. Ng, Martin Gutsche, Alois Gutmann, Bruno Spuler |
Plasma-etching processes for ULSI semiconductor circuits. |
IBM J. Res. Dev. |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Donna R. Cote, Son Van Nguyen, Anthony K. Stamper, Douglas S. Armbrust, Dirk Tobben, Richard A. Conti, Gill Yong Lee |
Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits. |
IBM J. Res. Dev. |
1999 |
DBLP DOI BibTeX RDF |
|
25 | D. Stroobannt |
PIN count prediction in ratio cut partitioning for VLSI and ULSI. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Eliane França |
Projeto de um circuito integrado dedicado a simulação de circuitos ULSI. |
|
1999 |
RDF |
|
25 | Hoan H. Pham, Arokia Nathan |
A new formulation for accurate numerical extraction of interconnect capacitance in ULSI. |
ICECS |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina |
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. |
IEEE J. Solid State Circuits |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami |
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. |
IEEE J. Solid State Circuits |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Hiroyuki Yamauchi, Hironori Akamatsu, Tsutomu Fujita |
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. |
IEEE J. Solid State Circuits |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango |
Standby/active mode logic for sub-1-V operating ULSI memory. |
IEEE J. Solid State Circuits |
1994 |
DBLP DOI BibTeX RDF |
|
25 | R. Kent Smith, William M. Coughran Jr. |
Computational Challenges in Simulations of ULSI Semiconductor Devices. |
HICSS (1) |
1994 |
DBLP BibTeX RDF |
|
25 | S. K. Lahiri 0001, M. K. Das, A. Das Gupta, I. Manna |
3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold Voltage. |
VLSI Design |
1994 |
DBLP DOI BibTeX RDF |
|
25 | Yoshiharu Ichikawa, Jun-ichiro Toriwaki |
A Digital ULSI Inspection Method Using Parallel Scanning Confocal Microscope. |
MVA |
1994 |
DBLP BibTeX RDF |
|
25 | Tadahiro Ohmi |
ULSI reliability through ultraclean processing. |
Proc. IEEE |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Mohamed Nekili, Yvon Savaria |
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
25 | Soo-Young Oh, Keh-Jeng Chang, Norman Chang, Ken Lee |
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. |
ICCD |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima |
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. |
ITC |
1992 |
DBLP DOI BibTeX RDF |
|
25 | Nobuhiro Tomabechi |
A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems. |
Syst. Comput. Jpn. |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Moshe Shahaf |
DesignFab: A Methodology for ULSI Microprocessor Design. |
ICCD |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Gopi Ganapathy, Jacob A. Abraham |
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. |
ITC |
1991 |
DBLP DOI BibTeX RDF |
|
25 | A. Reisman |
Ionizing radiation effects on ULSI device yield and reliability. |
J. Supercomput. |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Sandro Solmi, Renato Angelucci, Marco Merli |
Shallow junctions for ULSI technology. |
Eur. Trans. Telecommun. |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Arnaldo Hilário Viegas de Lima, Raul César B. Martins, Ronaldo Stern, Luiza Maria F. Carneiro |
GARDEN - An Integrated and Evolving Environment for ULSI/VLSI CAD Applications. |
IBM Syst. J. |
1989 |
DBLP DOI BibTeX RDF |
|
25 | F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin |
NOISY: an electrical noise checker for ULSI. |
ICCAD |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Md. Sajjad Rahaman, Masud H. Chowdhury |
BER performance comparison between CDMA and UWB for RF/wireless interconnect application. |
EIT |
2008 |
DBLP DOI BibTeX RDF |
|
16 | João M. S. Silva, Joel R. Phillips, Luís Miguel Silveira |
Efficient Representation and Analysis of Power Grids. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Saurabh Jain, W. Robert Daasch, David Armbrust |
Analyzing the Impact of Fault Tolerant BIST for VLSI Design. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Ray T. Chen |
Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
PCB interconnects, optical bus architecture, optical interconnects |
16 | Yiyu Shi 0001, Lei He 0001 |
Empire: an efficient and compact multiple-parameterized model order reduction method. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
reduction, sensitivity, parameter |
16 | Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl |
IntSim: A CAD tool for optimization of multilevel interconnect networks. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Impact of interconnect length changes on effective materials properties (dielectric constant). |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
performance, routing, interconnect, cycle time, interconnect model, rent, path delay |
16 | Zhe Feng 0002, Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan |
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
?-geometry, O(nlogn), Steiner tree construction, obstacle-avoiding |
16 | Qi Zhu 0002, Hai Zhou 0001, Tong Jing, Xianlong Hong, Yang Yang 0040 |
Spanning graph-based nonrectilinear steiner tree algorithms. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yu Hu 0002, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xiaodong Hu 0001, Guiying Yan |
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yin Wang, Xianlong Hong, Tong Jing, Yang Yang 0040, Xiaodong Hu 0001, Guiying Yan |
The polygonal contraction heuristic for rectilinear Steiner tree construction. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yaw-Jen Chang |
Fault Detection for Plasma Etching Processes Using RBF Neural Networks. |
ISNN (3) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
wire-length distribution model, routing, interconnect, rent |
16 | Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti |
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
load capacitance, routing, application specific integrated circuit (ASIC), clock, power dissipation |
16 | Joohyung Lee 0004, Yogesh B. Gianchandani |
A scanning thermal microscopy system with a temperature dithering, servo-controlled interface circuit. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Vijay K. Jain, Glenn H. Chapman |
Level-Hybrid Optoelectronic TESH Interconnection Network. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Abhisek Dixit, V. Ramgopal Rao |
A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier |
Few electron devices: towards hybrid CMOS-SET integrated circuits. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics |
16 | Gerard A. Allan |
Yield prediction by sampling IC layout. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Yi-Kan Cheng, David Bearden, Kanti Suryadevara |
Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|