Search results for "UltraSPARC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Martin Sandrieser, Sabri Pllana, Siegfried Benkner	Evaluation of the SUN UltraSparc T2+ Processor for Computational Science.	ICCS (1)	2009	DBLP DOI BibTeX RDF	Sun UltraSparc T2+, Niagara2, Evaluation, Computational Science
82	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
72	Spiros Kalogeropulos	An Enhanced Trace Scheduler for SPARC Processors.	Euro-Par	2003	DBLP DOI BibTeX RDF
67	Alexander Dalal, Lavi Lev, Sundari Mitra	Design of an efficient power distribution network for the UltraSPARC-I microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
67	Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor	Incas: a cycle accurate model of UltraSPARC.	ICCD	1995	DBLP DOI BibTeX RDF	cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification
56	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
56	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham	Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor.	MICRO	2005	DBLP DOI BibTeX RDF
56	Rita Yu Chen, Paul Yip, Georgios K. Konstadinidis, Andrew Demas, Fabian Klass, Robert E. Mains, Margaret Schmitt, Dina Bistry	Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design.	ICCD	2002	DBLP DOI BibTeX RDF
55	Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Thread to strand binding of parallel network applications in massive multi-threaded systems.	PPoPP	2010	DBLP DOI BibTeX RDF	ultrasparc t2, simultaneous multithreading, process scheduling, cmt
53	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon	A dual-core 64b ultraSPARC microprocessor for dense server applications.	DAC	2004	DBLP DOI BibTeX RDF	L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability
43	Jun Shirako, David M. Peixotto, Vivek Sarkar, William N. Scherer III	Phaser accumulators: A new reduction construct for dynamic parallelism.	IPDPS	2009	DBLP DOI BibTeX RDF
43	Myungho Lee, Brian Whitney, Nawal Copty	Performance and Scalability of OpenMP Programs on the Sun FireTM E25K Throughput Computing Server.	WOMPAT	2004	DBLP DOI BibTeX RDF
41	Anjali Kinra, Aswin Mehta, Neal Smith, Jackie Mitchell, Fred Valente	Diagnostic techniques for the UltraSPARC microprocessors.	ITC	1998	DBLP DOI BibTeX RDF
41	Marc E. Levitt	Designing UltraSparc for Testability.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
41	Andrew Over, Bill Clarke, Peter E. Strazdins	A Comparison of Two Approaches to Parallel Simulation of Multiprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF	speedup analysis, Sparc Sulima, UltraSPARC IIICu-based multiprocessor systems, careful locking, simulation time quantum, serial simulation, load-balancing, parallel simulation, parallel discrete event simulation, interconnect model, NAS parallel benchmarks
29	Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Rizos Sakellariou, Mateo Valero	FlexDCP: a QoS framework for CMP architectures.	ACM SIGOPS Oper. Syst. Rev.	2009	DBLP DOI BibTeX RDF
29	Shrenik Mehta, Dwayne Lee	Industry perspective on chip multi-threading, bridging the gap with academia using OpenSPARC.	WCAE	2007	DBLP DOI BibTeX RDF
29	Yonghong Song, Spiros Kalogeropulos, Partha Tirumalai	Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors.	IEEE PACT	2005	DBLP DOI BibTeX RDF
29	Spiros Kalogeropulos, Mahadevan Rajagopalan, Vikram Rao, Yonghong Song, Partha Tirumalai	Processor Aware Anticipatory Prefetching in Loops.	HPCA	2004	DBLP DOI BibTeX RDF
29	Kazuhisa Ishizaka, Takamichi Miyamoto, Jun Shirako, Motoki Obata, Keiji Kimura, Hironori Kasahara	Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers.	LCPC	2004	DBLP DOI BibTeX RDF
29	Neungsoo Park, Bo Hong, Viktor K. Prasanna	Tiling, Block Data Layout, and Memory Hierarchy Performance.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	Block data layout, TLB misses, memory hierarchy, tiling, cache misses
29	Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, Kevin Normoyle, Sutikshan Bhutani	Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor.	FORTE	2002	DBLP DOI BibTeX RDF
29	Anssi Huttunen, Irek Defée	Performance of desktop software MPEG-2 TS decoder.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
27	Yu Wang, Linda Wu, Jing Guo	Multi-Grain Parallel Accelerate System for H.264 Encoder on ULTRASPARC T2.	J. Comput.	2013	DBLP BibTeX RDF
27	Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini	UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
27	Lawrence Spracklen	Sun's 3rd generation on-chip UltraSPARC security accelerator.	Hot Chips Symposium	2009	DBLP DOI BibTeX RDF
27	Thomas A. Ziaja, Poh J. Tan	Efficient Array Characterization in the UltraSPARC T2.	VTS	2009	DBLP DOI BibTeX RDF
27	Georg Hager, Thomas Zeiser, Gerhard Wellein	Data Access Characteristics and Optimizations for Sun UltraSPARC T2 and T2+ Systems.	Parallel Process. Lett.	2008	DBLP DOI BibTeX RDF
27	Ishwar Parulkar, Sriram Anandakumar, Gaurav Agarwal, Gordon Liu, Krishna Rajan, Frank Chiu, Rajesh Pendurkar	DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor.	ITC	2008	DBLP DOI BibTeX RDF
27	Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen	Transition Test on UltraSPARC- T2 Microprocessor.	ITC	2008	DBLP DOI BibTeX RDF
27	Peter E. Strazdins, Bill Clarke, Andrew Over	Efficient Cycle-Accurate Simulation of the Ultrasparc III CPU.	ACSC	2007	DBLP BibTeX RDF
27	Joseph Antony, Pete P. Janes, Alistair P. Rendell	Exploring Thread and Memory Placement on NUMA Architectures: Solaris and Linux, UltraSPARC/FirePlane and Opteron/HyperTransport.	HiPC	2006	DBLP DOI BibTeX RDF
27	Ana Sonia Leon, Brian Langley, Jinuk Luke Shin	The UltraSPARC T1 Processor: CMT Reliability.	CICC	2006	DBLP DOI BibTeX RDF
27	P. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall	Testing of UltraSPARC T1 Microprocessor and its Challenges.	ITC	2006	DBLP DOI BibTeX RDF
27	Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon	A dual-core 64-bit ultraSPARC microprocessor for dense server applications.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
27	Adam Czezowski, Peter Christen	How Fast Is -Fast? Performance Analysis of KDD Applications Using Hardware Performance Counters on UltraSPARC-III.	AusDM	2002	DBLP BibTeX RDF
27	Hee-Tae Ahn, David J. Allstot	A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
27	Farideh Golshan	Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor.	ITC	2000	DBLP DOI BibTeX RDF
27	Tim Horel, Gary Lauterbach	UltraSPARC-III: designing third-generation 64-bit performance.	IEEE Micro	1999	DBLP DOI BibTeX RDF
27	Hee-Tae Ahn	A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor.	CICC	1999	DBLP DOI BibTeX RDF
27	Anjali Kinra	Towards reducing "functional only" fails for the UltraSPARC microprocessors.	ITC	1999	DBLP DOI BibTeX RDF
27	Kevin Normoyle, Michael A. Csoppenszky, Allan Tzeng, Timothy P. Johnson, Christopher D. Furman, Jamshid Mostoufi	UltraSPARC-II/: expanding the boundaries of a system on a chip.	IEEE Micro	1998	DBLP DOI BibTeX RDF
27	Ramesh Radhakrishnan, Lizy Kurian John	Execution characteristics of object oriented programs on the UltraSPARC-II.	HiPC	1998	DBLP DOI BibTeX RDF
27	Knut Omang	Performance of a Cluster of PCI Based UltraSparc Workstations Interconnected with SCI.	CANPC	1998	DBLP DOI BibTeX RDF
27	Marc Tremblay, J. Michael O'Connor	UltraSparc I: a four-issue processor supporting multimedia.	IEEE Micro	1996	DBLP DOI BibTeX RDF
27	Zhi-Jian (Alex) Mou, Daniel Rice, Wei Ding	VIS-based native video processing on UltraSPARC.	ICIP (2)	1996	DBLP DOI BibTeX RDF
27	Gary Goldman, Partha Tirumalai	UltraSPARC-II: The Advancement of UltraComputing.	COMPCON	1996	DBLP DOI BibTeX RDF
27	Partha Tirumalai, Dale Greenley, Boris Beylin, Krishna Subramanian 0003	UltraSPARC: Compiling for Maximum Floating-Point Performance.	COMPCON	1996	DBLP DOI BibTeX RDF
27	Marc Tremblay, Dale Greenley, Kevin Normoyle	The design of the microarchitecture of UltraSPARC-I.	Proc. IEEE	1995	DBLP DOI BibTeX RDF
27	Chang-Guo Zhou, Leslie Kohn, Daniel Rice, Ihtisham Kabir, Aman Jabbi, Xiao-Ping Hu	MPEG Video Decoding with the UltraSPARC Visual Instruction Set.	COMPCON	1995	DBLP DOI BibTeX RDF
27	Dale Greenley, J. Bauman, D. Chang, Dennis Chen, R. Eltejaein, Philip A. Ferolito, P. Fu, Robert B. Garner, D. Greenhill, H. Grewal, Kalon Holdbrook, B. Kim, Leslie Kohn, Hang Kwan, M. Levitt, Guillermo Maturana, D. Mrazek, Chitresh Narasimhaiah, Kevin Normoyle, N. Parveen, P. Patel, A. Prabhu, Marc Tremblay, Michelle Wong, L. Yang, Krishna Yarlagadda, Robert K. Yu, Robert Yung, Gregory B. Zyner	UltraSPARC: The Next Generation Superscalar 64-bit SPARC.	COMPCON	1995	DBLP DOI BibTeX RDF
27	Leslie Kohn, Guillermo Maturana, Marc Tremblay, A. Prabhu, Gregory B. Zyner	The Visual Instruction Set (VIS) in UltraSPARC.	COMPCON	1995	DBLP DOI BibTeX RDF
27	S. Mehta, S. Ahmed, S. Al-Ashari, Dennis Chen, Dev Chen, S. Cokmez, R. Eltejaein, P. Fu, Jeffery Gee, T. Granvold, Amaresh Iyer, A. K. Lin, Guillermo Maturana, D. McConn, H. Mohammed, Jamshid Mostoufi, A. Moudgal, Srinivas Nori, Gary Peterson, M. Splain, T. Yu	Verification of the UltraSPARC Microprocessor.	COMPCON	1995	DBLP DOI BibTeX RDF
27	James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong	UltraSPARC-I Emulation.	DAC	1995	DBLP DOI BibTeX RDF
27	Lawrence Yang, David Gao 0001, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein	System Design Methodology of UltraSPARC-I.	DAC	1995	DBLP DOI BibTeX RDF
27	A. Cao, A. Adalal, J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan, Manjunath Doreswamy, Philip A. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin, L. Lev, J. MacDonald, M. Ma, Samir Mitra, P. Patel, A. Prabhu, R. Puranik, S. Rozanski, N. Ross, P. Saggurti, Slobodan Simovich, R. Sunder, B. Sur, W. Vercruysse, Michelle Wong, P. Yip, Robert K. Yu, J. Zhou, Gregory B. Zyner	CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc.	DAC	1995	DBLP DOI BibTeX RDF
27	Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Leslie Kohn	A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I.	DAC	1995	DBLP DOI BibTeX RDF
26	Ruken Zilan, Javier Verdú, Jorge García-Vidal, Mario Nemirovsky, Rodolfo A. Milito, Mateo Valero	An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.	MASCOTS	2011	DBLP DOI BibTeX RDF	Fine grain modeling, a methodology to build simulators, a simulation tool for multiï¿½??levels of shared resource architecture modeling, UltraSPARC T2, queueing modeling
14	Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
14	Kamesh Madduri, David A. Bader	Compact graph representations and parallel connectivity algorithms for massive dynamic network analysis.	IPDPS	2009	DBLP DOI BibTeX RDF
14	Jun Shirako, Jisheng M. Zhao, V. Krishna Nandivada, Vivek Sarkar	Chunking parallel loops in the presence of synchronization.	ICS	2009	DBLP DOI BibTeX RDF	loop chunking, phasers, exceptions
14	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
14	Sabri Pllana, Siegfried Benkner, Eduard Mehofer, Lasse Natvig, Fatos Xhafa	Towards an Intelligent Environment for Programming Multi-core Computing Systems.	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
14	Georg Hager, Thomas Zeiser, Gerhard Wellein	Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Ayse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross	Proactive temperature balancing for low cost thermal management in MPSoCs.	ICCAD	2008	DBLP DOI BibTeX RDF
14	Jiaqi Zhang, Zhiyi Huang 0001, Wenguang Chen, Qihang Huang, Weimin Zheng	Maotai: View-Oriented Parallel Programming on CMT Processors.	ICPP	2008	DBLP DOI BibTeX RDF
14	Daniel Chen 0001, Gabriela Jacques-Silva, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Bruce G. Mealey	Error Behavior Comparison of Multiple Computing Systems: A Case Study Using Linux on Pentium, Solaris on SPARC, and AIX on POWER.	PRDC	2008	DBLP DOI BibTeX RDF
14	Tien-Hsiung Weng, Ruey-Kuen Perng, Barbara M. Chapman	OpenMP Implementation of SPICE3 Circuit Simulator.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	OpenMP SPICE circuit simulator, Shared-memory programming model
14	David A. Bader, Kamesh Madduri	A Graph-Theoretic Analysis of the Human Protein-Interaction Network Using Multicore Parallel Algorithms.	IPDPS	2007	DBLP DOI BibTeX RDF
14	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.	IPDPS	2007	DBLP DOI BibTeX RDF
14	Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos	Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
14	Paul A. Karger	Performance and security lessons learned from virtualizing the alpha processor.	ISCA	2007	DBLP DOI BibTeX RDF	virtualizability, security, virtual machine monitors, hypervisors
14	Jacqueline Chame, Chun Chen 0002, Pedro C. Diniz, Mary W. Hall, Yoon-Ju Lee, Robert F. Lucas	An overview of the ECO project.	IPDPS	2006	DBLP DOI BibTeX RDF
14	Dan Wallin, Henrik Löf, Erik Hagersten, Sverker Holmgren	Multigrid and Gauss-Seidel smoothers revisited: parallelization on chip multiprocessors.	ICS	2006	DBLP DOI BibTeX RDF	Gauss-Seidel, temporal blocking, CMP, OpenMP, relaxation, orderings, multigrid, Poisson equation, cache blocking
14	Wenduo Zhou, David K. Lowenthal	A Parallel, Out-of-Core Algorithm for RNA Secondary Structure Prediction.	ICPP	2006	DBLP DOI BibTeX RDF
14	Joseph Bonneau, Ilya Mironov	Cache-Collision Timing Attacks Against AES.	CHES	2006	DBLP DOI BibTeX RDF	cache, cryptanalysis, AES, side-channel attack, timing attack
14	Jason Hiser, Daniel W. Williams, Adrian Filipi, Jack W. Davidson, Bruce R. Childers	Evaluating fragment construction policies for SDT systems.	VEE	2006	DBLP DOI BibTeX RDF	dynamic translation performance, software dynamic translator, performance, low overhead
14	Paul Fearnhead	Direct simulation for discrete mixture distributions.	Stat. Comput.	2005	DBLP DOI BibTeX RDF	Bayesian model choice, binomial mixture, genetic linkage, Markov-dependent mixtures, Poisson mixture, particle filters, Forward-Backward algorithm
14	Paul C. van Oorschot, Anil Somayaji, Glenn Wurster	Hardware-Assisted Circumvention of Self-Hashing Software Tamper Resistance.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	self-hashing, operating system kernels, software protection, Tamper resistance, checksumming, application security, processor design
14	Andrew Over, Peter E. Strazdins, Bill Clarke	Cycle Accurate Memory Modelling: A Case-Study in Validation.	MASCOTS	2005	DBLP DOI BibTeX RDF
14	Chun Chen 0002, Jacqueline Chame, Mary W. Hall	Combining Models and Guided Empirical Search to Optimize for Multiple Levels of the Memory Hierarchy.	CGO	2005	DBLP DOI BibTeX RDF
14	Prasad Jayanti, Srdjan Petrovic	Efficiently Implementing a Large Number of LL/SC Objects.	OPODIS	2005	DBLP DOI BibTeX RDF
14	Glenn Wurster, Paul C. van Oorschot, Anil Somayaji	A Generic Attack on Checksumming-Based Software Tamper Resistance.	S&P	2005	DBLP DOI BibTeX RDF
14	Prasad Jayanti, Srdjan Petrovic	Efficiently Implementing LL/SC Objects Shared by an Unknown Number of Processes.	IWDC	2005	DBLP DOI BibTeX RDF
14	ManMohan S. Sodhi, Stephen Norris	A Flexible, Fast, and Optimal Modeling Approach Applied to Crew Rostering at London Underground.	Ann. Oper. Res.	2004	DBLP DOI BibTeX RDF	crew rostering, rota, cyclic graph, aggregation, decomposition, mixed-integer linear programming
14	Joon-Sang Park, Michael Penner, Viktor K. Prasanna	Optimizing Graph Algorithms for Improved Cache Performance.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Cache-friendly algorithms, shortest path, graph algorithms, minimum spanning trees, graph matching, algorithm performance, cache-oblivious algorithms, data layout optimizations
14	Michael Krietemeyer, Daniel Versick, Djamshid Tavangarian	A Mathematical Model for the Transitional Region Between Cache Hierarchy Levels.	IICS	2004	DBLP DOI BibTeX RDF
14	Rodric M. Rabbah, Krishna V. Palem	Data remapping for design space optimization of embedded memory systems.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	data remapping, embedded systems, caches, memory hierarchy, Design space exploration, compiler optimization, memory subsystem
14	José Carlos Rodríguez-Rodríguez, Alexis Quesada-Arencibia, Roberto Moreno-Díaz Jr., K. Nicholas Leibovic	On Parallel Channel Modeling of Retinal Processes.	EUROCAST	2003	DBLP DOI BibTeX RDF
14	Alan E. Charlesworth	The Sun Fireplane Interconnect.	IEEE Micro	2002	DBLP DOI BibTeX RDF
14	Daisuke Takahashi	A Blocking Algorithm for Parallel 1-D FFT on Shared-Memory Parallel Computers.	PARA	2002	DBLP DOI BibTeX RDF
14	Toshio Endo, Kenjiro Taura	Reducing pause time of conservative collectors.	MSP/ISMM	2002	DBLP DOI BibTeX RDF	memory management, concurrent garbage collection, parallel garbage collection, conservative garbage collection
14	Ali Akoglu, Aravind Dasu, Arvind Sudarsanam, Mayur Srinivasan, Sethuraman Panchanathan	Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing.	IPDPS	2002	DBLP DOI BibTeX RDF	reconfigurable media processor, recurring pattern analyzer, mobile multimedia processing, partition, dynamic reconfiguration, reconfigurable architectures, data flow graph, control flow graph, MPEG4, hardware software co-design, hardware software partitioning, routing architecture
14	Joon-Sang Park, Michael Penner, Viktor K. Prasanna	Optimizing Graph Algorithms for Improved Cache Performance.	IPDPS	2002	DBLP DOI BibTeX RDF
14	Hiran Tennakoon, Carl Sechen	Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.	ICCAD	2002	DBLP DOI BibTeX RDF
14	Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar 0002	A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors.	ITC	2002	DBLP DOI BibTeX RDF
14	C.-J. Richard Shi, Sheldon X.-D. Tan	Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
14	Ismail Kadayif, T. Chinoda, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam	vEC: virtual energy counters.	PASTE	2001	DBLP DOI BibTeX RDF	system energy consumption, optimizations, embedded systems, signal processing, hardware performance counters
14	Daisuke Takahashi	A Blocking Algorithm for FFT on Cache-Based Processors.	HPCN	2001	DBLP DOI BibTeX RDF
14	Perry Cheng, Guy E. Blelloch	A Parallel, Real-Time Garbage Collector.	PLDI	2001	DBLP DOI BibTeX RDF