Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
86	Mario Kovac, N. Ranganathan	JAGUAR: a high speed VLSI chip for JPEG image compression standard.	VLSI Design	1995	DBLP DOI BibTeX RDF	JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
74	David Hertweck, Mihaela Nica, Sang-Eon Park, Carla N. Purdy	Standard Data Representations for VLSI Algorithm Development.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	VLSi design, benchmarking, graph partitioning, VLSI algorithms
73	S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri	A VLSI chip for image compression using variable block size segmentation.	ICCD	1996	DBLP DOI BibTeX RDF	variable block size segmentation, VBSS scheme, variable size blocks, redundancy features, maximum compression, nearest neighbor communication, CMOS VLSI chip, image characteristics extraction subsystem, Cadence design tools, VLSI, parallelism, pipelining, image compression, VLSI architecture, VLSI implementation, lossless image compression, VLSI chip, coding techniques
73	Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
68	Wallace B. Leigh	A personal computer based VLSI design curriculum.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design curriculum, teaching institutions, capstone VLSI course, analog design course, digital design synthesis course, teaching curriculum, VLSI, design methodology, integrated circuit design, circuit CAD, personal computers, computer aided instruction, microcomputer applications, electronic engineering education
68	Jens Lienig	Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach.	VLSI Design	1997	DBLP DOI BibTeX RDF	minimized crosstalk, interconnection routing, interconnection crosstalk, VLSI channel routing, VLSI switchbox routing, distributed workstation network, VLSI, VLSI design, parallel genetic algorithm
64	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
63	Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar	Routing using implicit connection graphs [VLSI design.	VLSI Design	1996	DBLP DOI BibTeX RDF	implicit connection graphs, shortest path related problems, minimum spanning tree problem, sparse strong connection graph, large VLSI design applications, VLSI, graph theory, search problems, circuit layout CAD, VLSI layout, integrated circuit layout, obstacles, search behavior
63	John A. Chandy, Prithviraj Banerjee	Parallel simulated annealing strategies for VLSI cell placement.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement
63	Luca Penzo, Donatella Sciuto, Cristina Silvano	VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.	VLSI Design	1995	DBLP DOI BibTeX RDF	odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits
63	Hossein Sahabi, Anup Basu, Mark Fiala	VLSI implementation of variable resolution image compression.	VLSI Design	1995	DBLP DOI BibTeX RDF	variable resolution image compression, bandwith requirements, telepresence system, teleconferencing systems, encoding/decoding subsystem, SBus interface, VLSI codec chip, real time compression, real time decompression, video rates, output image quality, 1024 pixel, 1048576 pixel, real-time systems, VLSI, data compression, image coding, teleconferencing, image resolution, video signal processing, digital signal processing chips, VLSI implementation, codecs, video codecs
60	Robert W. Brodersen	Implications of VLSI technology for speech processing.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
60	Robert Pearson	Linking fabrication and parametric testing to VLSI design courses.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design courses, simulation model parameters, VLSI, integrated circuit testing, integrated circuit design, integrated circuit modelling, educational courses, device models, parametric testing, electronic engineering education
60	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
60	S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy	Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements.	VLSI Design	1995	DBLP DOI BibTeX RDF	very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects
59	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
55	Ron Lin	Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes.	VLSI Design	1997	DBLP DOI BibTeX RDF	shift switching, asynchronous VLSI comparator, precharged CMOS domino logic, VLSI, semaphore
55	Kamran Eshraghian	Opto-VLSI Systems for Multimedia Computing.	VLSI Design	1997	DBLP DOI BibTeX RDF	opto-VLSI systems, online compression, online coding, VLSI, multimedia computing, processing capability, image capture
55	Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya	Geometric bipartitioning problem and its applications to VLSI.	VLSI Design	1996	DBLP DOI BibTeX RDF	geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
55	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
55	Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak	Syndrome signature in output compaction for VLSI BIST.	VLSI Design	1996	DBLP DOI BibTeX RDF	syndrome signature, output compaction, VLSI BIST, input patterns, n-input combinational circuit, primary syndrome, subsyndromes, subfunctions, single-output circuit, multiple output, VLSI, logic testing, data compression, built-in self test, integrated circuit testing, combinational circuits, switching functions, exhaustive testing
55	Sukumar Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
55	Giuseppe Ascia, Vincenzo Catania	Design of a VLSI parallel processor for fuzzy computing.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit
55	D. V. Poornaiah, P. V. Ananda Mohan	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron
55	Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality
55	Anoop Singhal, Chi-Yuan Lo	Object oriented data modeling for VLSI/CAD.	VLSI Design	1995	DBLP DOI BibTeX RDF	design data manager, integrated CAD system, modular program architecture, VLSI, object-oriented methods, integrated circuit design, circuit CAD, object oriented data modeling, VLSI CAD
52	N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A VLSI array architecture with dynamic frequency clocking.	ICCD	1996	DBLP DOI BibTeX RDF	VLSI array architecture, dynamic frequency clocking, linear VLSI array processor, DFLAP, power requirements, image processing, VLSI, throughput
51	Adger E. Harvin III, José G. Delgado-Frias	A Dictionary Machine Emulation on a VLSI Computing Tree System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	tree architectures, VLSI, data structure, pipeline computing, bit-serial, Dictionary machines
51	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
51	Chuan-Yu Wang, Kaushik Roy 0001	Maximum power estimation for CMOS circuits using deterministic and statistic approaches.	VLSI Design	1996	DBLP DOI BibTeX RDF	maximum power estimation, deterministic approach, instantaneous power consumption, ATG technique, Monte Carlo based technique, computational complexity, VLSI, lower bound, statistical analysis, automatic testing, circuit analysis computing, Monte Carlo methods, automatic test generation, VLSI circuits, CMOS circuits, CMOS digital integrated circuits, statistic approach
51	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
51	Luis A. Montalvo, Alain Guyot	Svoboda-Tung division with no compensation.	VLSI Design	1995	DBLP DOI BibTeX RDF	Svoboda-Tung division, radix-b division algorithm, iteration overflow, most significant digits, radix-b algorithm, IEEE normalised divisor, pre-scaling technique, stepwise approximation, VLSI, iterative methods, digital arithmetic, VLSI implementation, prescalers, dividing circuits
50	Subarna Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri	A VLSI architecture for cellular automata based parallel data compression.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel data compression, nongroup CA, VLSI, parallel architectures, data compression, cellular automata, cellular automata, VLSI architecture, state transition
50	Anthony D. Johnson	On locally optimal breaking of nondisjoint cyclic vertical constraints in VLSI channel routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally optimal breaking strategy, nondisjoint cyclic vertical constraints, VLSI channel routing, vertical constraint graph, nondisjoint circuits, common vertex, common path, channel router heuristics, automatic routers, interactive routers, VLSI, graph theory, parallel architectures, network routing, circuit layout CAD, integrated circuit layout
50	Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak	An improved output compaction technique for built-in self-test in VLSI circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits
50	Vincenzo Catania, Marco Russo	Analog gates for a VLSI fuzzy processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI fuzzy processor, synchronous fuzzy circuits, high noise immunity, fuzzy gates, VLSI, fuzzy logic, CMOS logic circuits, CMOS technology, logic gates, analogue processing circuits
50	Meenakshisundaram Gopi, Swami Manohar	A VLSI architecture for the computation of NURBS patches.	VLSI Design	1995	DBLP DOI BibTeX RDF	NURBS patches, nonuniform rational B-spline, interactive modeling session, patch generation, complete hardware solution, VLSI, computational geometry, parallel architectures, computer graphics, geometric modeling, VLSI architecture, splines (mathematics), B-spline curves
50	P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya	VLSI floorplan generation and area optimization using AND-OR graph search.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
50	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang	Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, VLSI circuits process for mixed-signal VLSI in a die size measuring 2.2 mm x 2.2 mm, low-power, microprocessor, RF
48	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa	VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
48	Minesh I. Patel, N. Ranganathan	A VLSI System Architecture For Real-Time Intelligent Decision Making.	ASAP	1996	DBLP DOI BibTeX RDF	VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays
47	Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu	Extending VLSI design with higher-order logic.	ICCD	1995	DBLP DOI BibTeX RDF	Cambridge Higher-Order Logic theorem-prover, microprogram sequencer, Am2910, VLSI, formal verification, formal verification, logic testing, theorem proving, logic design, logic CAD, VLSI design, higher-order logic, theorem-prover, design environment, instruction-set architecture, VLSI CAD
47	Wu Jigang, Thambipillai Srikanthan	A Run-time Reconfiguration Algorithm for VLSI Arrays.	VLSI Design	2003	DBLP DOI BibTeX RDF	Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
47	Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan	VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images.	VLSI Design	2003	DBLP DOI BibTeX RDF	Image Processing, VLSI, Watermarking, ASIC design
47	José G. Delgado-Frias, Richard Diaz	A VLSI Self-Compacting Buffer for DAMQ Communication Switches.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	dynamically allocated multi-queue, Communication buffer management, VLSI, Communication Switches
47	Anthony D. Johnson	Local Optimality Theory in VLSI Channel Routing: Composite Cyclic Vertical Constraints.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	vertical constraints, VLSI, theory, local optimality, Channel Routing
47	Gert Cauwenberghs	Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator.	VLSI Design	1998	DBLP DOI BibTeX RDF	neural networks, reinforcement learning, analog VLSI, delta-sigma modulation, analog-to-digital conversion
47	S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein	VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.	VLSI Design	1998	DBLP DOI BibTeX RDF	Fast counter, VLSI, Testability
46	Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal	An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.	VLSI Design	1997	DBLP DOI BibTeX RDF	three-layer restricted dogleg routing model, nontrivial lower bound, channel routing problem, two-layer Manhattan routing model, three-layer no-dogleg HVH routing model, two-layer restricted dogleg routing model, vertical constraint graph, VLSI, polynomial time algorithm, VLSI design
46	Nikolaos G. Bourbakis, Mohammad Mortazavi	An efficient building block layout methodology for compact placement.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
46	S. C. Prasad, Kaushik Roy 0001	Circuit optimization for minimisation of power consumption under delay constraint.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, internal capacitances, series-connected transistors, multipass algorithm, transistor reordering, VLSI, delays, logic design, logic CAD, circuit layout CAD, CMOS logic circuits, minimisation, circuit optimisation, integrated circuit layout, VLSI circuits, logic gates, capacitance, circuit optimization, delay constraint, CMOS gates
46	C. P. Ravikumar, Hemant Joshi	HISCOAP: a hierarchical testability analysis tool.	VLSI Design	1995	DBLP DOI BibTeX RDF	HISCOAP, hierarchical testability analysis tool, SCOAP measure, gate-level netlist, SCOAP expression diagrams, VLSI, logic testing, controllability, controllability, sequential circuits, sequential circuits, combinational circuits, combinational circuits, observability, observability, circuit analysis computing, integrated logic circuits, VLSI circuits, functional modules, stuck at fault model
46	Srimat T. Chakradhar	Optimum retiming of large sequential circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	optimum retiming, large sequential circuits, unit delay model, optimum clock period, path graph, VLSI, linear programming, delays, timing, integer programming, sequential circuits, logic CAD, integer linear program, flip-flops, circuit CAD, fast algorithm, integrated logic circuits, circuit optimisation, VLSI circuits, linear program relaxation
46	Ali Skaf, Alain Guyot	SAGA: the first general-purpose on-line arithmetic co-processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA
46	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
46	Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri	Board level fault diagnosis using cellular automata array.	VLSI Design	1995	DBLP DOI BibTeX RDF	board level fault diagnosis, cellular automata array, output responses, encoding strategy, byte error correcting code, encoded symbols, decoding structure, VLSI, fault diagnosis, logic testing, cellular automata, error correction codes, VLSI implementation, test vectors
46	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
45	Hasliza A. Rahim, Ab Al-Hadi Ab Rahman, R. Badlishah Ahmad, Wan Nur Suryani Firuz Wan Ariffin, Muhammad Imran Ahmad	The Performance Study of Two Genetic Algorithm Approaches for VLSI Macro-Cell Layout Area Optimization.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Steady-State Algorithm, Genetic Algorithm, VLSI, Area Optimization, Simple Genetic Algorithm
44	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
44	Catherine H. Gebotys, Robert J. Gebotys	Optimized mapping of video applications to hardware-software for VLSI architectures.	HICSS (1)	1995	DBLP DOI BibTeX RDF	integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor
44	Michael Yang, Ahmed N. Tantawy	A design methodology for protocol processors.	FTDCS	1995	DBLP DOI BibTeX RDF	protocol processors, FCS, Fibre Channel Standard, homogeneous multi-processors, single VLSI chip, VHDL macro libraries, VLSI protocol processors, CVDS, Communication VLSI Design System, protocols, asynchronous transfer mode, ATM, multiprocessing systems, communication protocols
43	Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada	A practical approach to instruction-based test generation for functional modules of VLSI processors.	VTS	1997	DBLP DOI BibTeX RDF	VLSI processors, instruction-based test generation, functional test pattern generation, gate level faults, constrained test generation, ALU oriented test pattern generation system, VLSI, functional modules, ALPS
43	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors.	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
43	Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst	Silicon VLSI processing architectures incorporating integrated optoelectronic devices.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
43	Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin	A Nanosensor Array-Based VLSI Gas Discriminator.	VLSI Design	2005	DBLP DOI BibTeX RDF
43	Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla	Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
43	V. Sankara Subramanian, C. P. Ravikumar	Estimating Crosstalk From Vlsi Layouts.	VLSI Design	2001	DBLP DOI BibTeX RDF
43	Von-Kyoung Kim, Tom Chen 0001, Mick Tegethoff	Fault Coverage Estimation for Early Stage of VLSI Design.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
43	Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya	Partitioning VLSI Floorplans by Staircase Channels for Global Routing.	VLSI Design	1998	DBLP DOI BibTeX RDF	maxflow-mincut, algorithms, complexity, partitioning, NP-completeness, Global routing
43	Fabio Ancona, Alessandro De Gloria, Rodolfo Zunino	Parallel VLSI Architectures for Cryptographic Systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
43	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
43	Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele	A flexible VLSI architecture for variable block size segment matching with luminance correction.	ASAP	1997	DBLP DOI BibTeX RDF	flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards
43	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
43	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
42	Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis 0001	A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.	VLSI-SoC (Selected Papers)	2006	DBLP DOI BibTeX RDF
42	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang	Novel Design for Testability of a Mixed-Signal VLSI IC.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, verification, microprocessor, testability, RF
42	Ranjeet Ranade, Sanjay Bhandari, A. N. Chandorkar	VLSI Implementation of Artificial Neural Network Based Digital Multiplier and Adder.	VLSI Design	1996	DBLP DOI BibTeX RDF	Digital Multiplier and Adder, VLSI Implementation of Neural Networks, Artificial Neural Networks (ANN)
42	Hartmut Schmeck, Heiko Schröder 0001	Dictionary Machines for Different Models of VLSI.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	VLSI hardware models, Dictionary machines. are taken as an example to demonstrate the implications the choice of the VLSI hardware model has on the design and analysis of algorithms and special purpose architectures, A systolic search tree and a two-dimensional systolic array are used to implement the dictionary machine, If the wire lengths only affect the area, the systolic search tree suggests itself as an efficient realization of a dictionary machine having constant period, linear areS and logarithmic execution t, Algorithms for VLSI, systolic search tree, systolic array, VLSI complexity, dictionary machine
42	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
42	Sandip Das 0001, Bhargab B. Bhattacharya	Channel routing in Manhattan-diagonal model.	VLSI Design	1996	DBLP DOI BibTeX RDF	Manhattan-diagonal model, layout grid, cyclic vertical constraints, low via count, reduced wire length, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, channel routing, output-sensitive algorithm
42	Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, Aman Sureka	OPRON: a new approach to planar OTC routing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	OPRON, planar OTC routing, planar over-the-cell routing, VLSI, dynamic programming, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, dynamic programming algorithm
42	James M. Varanelli, James P. Cohoon	A two-stage simulated annealing methodology.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	two-stage simulated annealing methodology, starting temperature determination, problem suite, VLSI, VLSI, formal method, simulated annealing, CAD, integrated circuit design, circuit CAD, optimization problems, circuit optimisation, running time, adaptive schedules, stop criterion
42	Ali Assi 0001, Bozena Kaminska	Modeling of communication protocols in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards
42	Ines Peters, Paul Molitor	Priority driven channel pin assignment.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	polynomial time improvement, linear channel pin assignment, LCPA algorithms, minimum channel density, vertical constraints, priority driven channel pin assignment, channel height, computational complexity, VLSI, VLSI, network routing, circuit layout CAD, running time, integrated circuit layout, priority schedule, channel routing
42	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
42	Rajat Kumar Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal	A general graph theoretic framework for multi-layer channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph theoretic framework, multilayer channel routing, track assignment, total wire length minimisation, two-layer VH routing model, three-layer HVH routing model, VLSI, graph theory, heuristics, network routing, circuit layout CAD, minimisation, VLSI layout, integrated circuit layout
42	Raj S. Mitra, Partha S. Roop, Anupam Basu	Implementation of design functions by available devices: a new algorithm.	VLSI Design	1995	DBLP DOI BibTeX RDF	design functions, available devices, function behaviors, mapping process, VLSI, VLSI, CAD, finite state machines, finite state machines, logic CAD, circuit CAD, logic partitioning, logic partitioning
42	Saibal Das, Sanjeev Saxena	Parallel algorithms for single row routing in narrow streets.	VLSI Design	1995	DBLP DOI BibTeX RDF	narrow streets, optimal layout, parallel algorithms, parallel algorithms, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, single row routing, IC design, CREW PRAM, tree machine
42	Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal	Computing area and wire length efficient routes for channels.	VLSI Design	1995	DBLP DOI BibTeX RDF	area efficient routes, wire length efficient routes, total wire length reduction, multilayer routing solutions, computational complexity, VLSI, NP-hard, polynomial time algorithms, network routing, circuit layout CAD, minimisation, VLSI layout, integrated circuit layout, channel routing
42	Khushro Shahookar, Pinaki Mazumder	Genetic multiway partitioning.	VLSI Design	1995	DBLP DOI BibTeX RDF	genetic multiway partitioning, result quality, binary chromosome, bit-mask operations, net cut evaluation, MCNC benchmark circuits, cut size, genetic algorithms, VLSI, VLSI, CAD, software tools, software tool, logic CAD, mutation, circuit CAD, crossover, cellular arrays, cost function, circuit optimisation, logic partitioning, multiple objectives, bipartitioning
42	Dinesh Bhatia, James Haralambides	Resource requirements for field programmable interconnection chips.	VLSI Design	1995	DBLP DOI BibTeX RDF	field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network
42	Andrew Lim 0001, Sartaj K. Sahni, Venkat Thanvantri	A fast algorithm to test planar topological routability.	VLSI Design	1995	DBLP DOI BibTeX RDF	planar topological routability testing, pin nets, single layer routing, IC layout design, VLSI, network topology, network routing, circuit layout CAD, fast algorithm, VLSI layout, integrated circuit layout, linear time algorithm
40	Zhong-Li He, Ming Lei Liou	Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
40	Li-Rong Zheng 0001, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
39	John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez	Validating fault tolerant designs using laser fault injection (LFI).	DFT	1997	DBLP DOI BibTeX RDF	fault tolerant designs validation, laser fault injection, VHSIC technology, in situ testing, transient error conditions, VLSI, faults, automated testing, transient, VLSI technology
39	Shantanu Dutt, Wenyong Deng	VLSI circuit partitioning by cluster-removal using iterative improvement techniques.	ICCAD	1996	DBLP DOI BibTeX RDF	ACM/SIGDA benchmark circuits, Fiduccia-Mattheyses algorithm, VLSI circuit partitioning, cluster-removal, iterative improvement techniques, look-ahead algorithm, partition quality, spectral partitioner MELO, VLSI, CAD
39	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
39	Gert Cauwenberghs	Bit-serial bidirectional A/D/A conversio.	ARVLSI	1995	DBLP DOI BibTeX RDF	digital-analogue conversion, bidirectional bit-serial convertor, algorithmic DAC conversion, successive approximation ADC, D/A conversion, fault-tolerant VLSI architecture, matched monotonic characteristics, 200 muW, 20 mus, VLSI, CMOS integrated circuits, analogue-digital conversion, integrated circuit reliability, A/D conversion, 2 micron, CMOS process
39	Fadi J. Kurdahi, Nikil D. Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
39	Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models