Search results for "VLSI-Design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Si-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar	Routing using implicit connection graphs [VLSI design.	VLSI Design	1996	DBLP DOI BibTeX RDF	implicit connection graphs, shortest path related problems, minimum spanning tree problem, sparse strong connection graph, large VLSI design applications, VLSI, graph theory, search problems, circuit layout CAD, VLSI layout, integrated circuit layout, obstacles, search behavior
61	Luca Penzo, Donatella Sciuto, Cristina Silvano	VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.	VLSI Design	1995	DBLP DOI BibTeX RDF	odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits
61	Fadi J. Kurdahi, Nikil D. Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
60	Jens Lienig	Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach.	VLSI Design	1997	DBLP DOI BibTeX RDF	minimized crosstalk, interconnection routing, interconnection crosstalk, VLSI channel routing, VLSI switchbox routing, distributed workstation network, VLSI, VLSI design, parallel genetic algorithm
56	Debasri Saha, Susmita Sur-Kolay	Encoding of Floorplans through Deterministic Perturbation.	VLSI Design	2009	DBLP DOI BibTeX RDF
54	Prathima Agrawal, Balakrishnan Narendran, Narayanan Shivakumar	Multi-way partitioning of VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	multi-way partitioning, hierarchical design processes, nets cut metric, VLSI, delays, economics, logic CAD, VLSI layout, integrated circuit layout, VLSI circuits, logic partitioning, minimisation of switching nets, average delay, integrated circuit manufacture, cost metric
54	Rajiv V. Joshi, Kaushik Roy 0001	Design of Deep Sub-Micron CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF
52	Kuo-Hsing Cheng, Shun-Wen Cheng	Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	full-swing logic, Low power design, VLSI design, hybrid logic, prime implicant
51	Shekhar Borkar	VLSI Design Challenges for Gigascale Integration.	VLSI Design	2005	DBLP DOI BibTeX RDF
51	Biswadip Mitra	Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
51	Masahiro Fujita	Formal Verification of C Language Based VLSI Designs.	VLSI Design	2004	DBLP DOI BibTeX RDF
51	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
50	Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra	Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications.	VLSI Design	2000	DBLP DOI BibTeX RDF	ATSC standard, picture processing, VLSI design, video processing, Digital television, HDTV, media processor
50	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
50	Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal	An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.	VLSI Design	1997	DBLP DOI BibTeX RDF	three-layer restricted dogleg routing model, nontrivial lower bound, channel routing problem, two-layer Manhattan routing model, three-layer no-dogleg HVH routing model, two-layer restricted dogleg routing model, vertical constraint graph, VLSI, polynomial time algorithm, VLSI design
50	Jin-Tai Yan	A simple yet effective genetic approach for the orientation assignment on cell-based layout.	VLSI Design	1996	DBLP DOI BibTeX RDF	genetic approach, orientation assignment, cell-based layout, total wire length minimisation, placement phase, routing area reduction, orientation states, vertical orientation bit, horizontal orientation bit, genetic algorithms, VLSI, VLSI design, network routing, circuit layout CAD, integrated circuit layout
50	John A. Chandy, Prithviraj Banerjee	Parallel simulated annealing strategies for VLSI cell placement.	VLSI Design	1996	DBLP DOI BibTeX RDF	parallel simulated annealing strategies, VLSI cell placement, cell placement annealing, multiple Markov chains, parallel moves approach, parallel algorithms, VLSI, simulated annealing, Markov processes, VLSI design, circuit layout CAD, integrated circuit layout, speculative computation, standard cell placement
50	Arun Balakrishnan, Srimat T. Chakradhar	Partial scan design for technology mapped circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	technology mapped circuits, scan flip-flops selection, multiple memory elements, library block, integer linear program formulation, production VLSI circuits, VLSI, graph theory, linear programming, design for testability, integer programming, logic design, logic CAD, VLSI design, flip-flops, integrated circuit design, circuit CAD, integrated logic circuits, functional specifications, partial scan design
49	Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam	Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.	VLSI Design	2009	DBLP DOI BibTeX RDF
49		VLSI Design 2005 Conference Awards.	VLSI Design	2006	DBLP DOI BibTeX RDF
49		Call for Participation: 10th IEEE VLSI Design & Test Symposium.	VLSI Design	2006	DBLP DOI BibTeX RDF
49		VLSI Design 2006 Conference Awards.	VLSI Design	2006	DBLP DOI BibTeX RDF
49		VLSI Design Conference History.	VLSI Design	2006	DBLP DOI BibTeX RDF
49		Call for Participation: VLSI Design 2007.	VLSI Design	2006	DBLP DOI BibTeX RDF
49	A. Vasudevan	Advances in VLSI Design and Product Development Challenges.	VLSI Design	2003	DBLP DOI BibTeX RDF
49	Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar	Theory and Applications of Cellular Automata for VLSI Design and Testing.	VLSI Design	2000	DBLP DOI BibTeX RDF
49	Debashis Saha, Anantha P. Chandrakasan	Web-based Distributed VLSI Design.	VLSI Design	1998	DBLP DOI BibTeX RDF
49	Gary William Grewal, Thomas Charles Wilson	An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.	VLSI Design	1997	DBLP DOI BibTeX RDF
49	Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti 0001, S. C. De Sarkar	Multiobjective Search in VLSI Design.	VLSI Design	1994	DBLP DOI BibTeX RDF
49	Tanuj Bagchi, Sajal K. Das 0001	An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design.	VLSI Design	1994	DBLP DOI BibTeX RDF
49	Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri	Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders.	VLSI Design	1994	DBLP DOI BibTeX RDF
49	Mourad B. Takla, Donald W. Bouldin, Daniel B. Koch	Early Exploration of the Multi-Dimensional VLSI Design Space.	VLSI Design	1994	DBLP DOI BibTeX RDF
49	Joseph B. Costello	On the Brink of a New Era in VLSI Design.	VLSI Design	1994	DBLP BibTeX RDF
49	Sunil D. Sherlekar	Export of VLSI Design and CAD: Present and Future.	VLSI Design	1993	DBLP BibTeX RDF
49	G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien	Area Efficient VLSI Design with Cells of Controllable Complexity.	VLSI Design	1993	DBLP DOI BibTeX RDF
49	Osamu Karatsu	On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective.	VLSI Design	1993	DBLP DOI BibTeX RDF
48	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
48	Vineet Sahula, C. P. Ravikumar	The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.	VLSI Design	2001	DBLP DOI BibTeX RDF
47	Pranav Anbalagan, Jeffrey A. Davis	Maximum Multiplicity Distributions for Length Prediction Driven Placement.	VLSI Design	2004	DBLP DOI BibTeX RDF
46	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
46	C. P. Ravikumar	Multiprocessor Architectures for Embedded System-on-chip Applications.	VLSI Design	2004	DBLP DOI BibTeX RDF
46	Marong Phadoongsidhi, Kewal K. Saluja	Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
46	Chunhong Chen	Probabilistic Analysis of Rectilinear Steiner Trees.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
46	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind	An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
45	Juha Plosila, Tiberiu Seceleanu	Design of Synchronous Action Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF
45	Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag	Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.	VLSI Design	1999	DBLP DOI BibTeX RDF
44	Tuhina Samanta, Hafizur Rahaman 0001, Prasun Ghosal, Parthasarathi Dasgupta	A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.	VLSI Design	2009	DBLP DOI BibTeX RDF
44	Charbel J. Akl, Magdy A. Bayoumi	Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
44	Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.	VLSI Design	2009	DBLP DOI BibTeX RDF
44	Jiajin Tu, Jian Chen 0030, Lizy K. John	Hardware Efficient Piecewise Linear Branch Predictor.	VLSI Design	2007	DBLP DOI BibTeX RDF
44	Kolin Paul, Dipanwita Roy Chowdhury	Application of GF(2p) CA in Burst Error Correcting Codes.	VLSI Design	2000	DBLP DOI BibTeX RDF
44	Natesan Venkateswaran, Dinesh Bhatia	Clock-Skew Constrained Cell Placement.	VLSI Design	1996	DBLP DOI BibTeX RDF
41		18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India	VLSI Design	2005	DBLP BibTeX RDF
41	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Tejasvi Das, Clyde Washburn, P. R. Mukund, Steve Howard, Ken Paradis, Jung-Geau Jang, Jan Kolnik, Jeff Burleson	Effects of Technology and Dimensional Scaling on Input Loss Prediction of RF MOSFETs.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Manish Garg, Laurent Le Cam, Matthieu Gonzalez	Lithography Driven Layout Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Vishak Venkatraman, Wayne P. Burleson	Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Yervant Zorian	Optimizing SoC Manufacturability.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Sachin Shrivastava, Sreeram Chandrasekar	Crosstalk Noise Analysis at Multiple Frequencies.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Arindam Basu, Anindya Sundar Dhar	Design Issues in Switched Capacitor Ladder Filters.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Muhammad Arsalan, Maitham Shams	Charge-Recovery Power Clock Generators for Adiabatic Logic Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev	Off-Line Testing of Asynchronous Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Nagendran Rangan, Karam S. Chatha	A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee	Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran	Rapid Embedded Hardware/Software System Generation.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Sheng Zhang 0008, Sharad C. Seth, Bhargab B. Bhattacharya	On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das	Cellular Automata Based Test Structures with Logic Folding.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Aditya Sankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby	Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Biranchinath Sahu, Gabriel A. Rincón-Mora	A High-Efficiency, Dual-Mode, Dynamic, Buck-Boost Power Supply IC for Portable Applications.	VLSI Design	2005	DBLP DOI BibTeX RDF	Buck-boost converter IC, integrated power management, dual-mode converter
41	N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell	The Impact of Inductance on Transients Affecting Gate Oxide Reliability.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Parthasarathi Dasgupta	Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Rajarshi Paul, Amit Patra, Shailendra Baranwal, Kaushik Dash	Design of Second-Order Sub-Bandgap Mixed-Mode Voltage Reference Circuit for Low Voltage Applications.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury	An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Alan Naumann	ESL - The Next Leadership Opportunity for India?	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Krishnan Srinivasan, Karam S. Chatha	ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan	Memory-Centric Motion Estimator.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Shabbir H. Batterywala, Madhav P. Desai	Variance Reduction in Monte Carlo Capacitance Extraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta 0001	Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Sayantan Das 0001, Ansuman Banerjee, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti 0001, Chunduri Rama Mohan, Limor Fix	Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Andreas Hoffmann 0002, Frank Fiedler, Achim Nohl, Surender Parupalli	A Methodology and Tooling Enabling Application Specific Processor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF	SIMD, VLIW, ASIP
41	Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal	Evaluation of Speed and Area of Clustered VLIW Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin	Implementing LDPC Decoding on Network-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Aarti Gupta, Malay K. Ganai, Pranav Ashar	Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Frank Sill, Frank Grassert, Dirk Timmermann	Reducing Leakage with Mixed-V_th (MVT).	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Chih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi	A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	K. Uday Bhaskar, M. Prasanth, G. Chandramouli, V. Kamakoti 0001	A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Yuanzhong Wan, Maitham Shams	Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri	Non-Manhattan Routing Using a Manhattan Router.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea	Recent Advances in Verification, Equivalence Checking and SAT-Solvers.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Janick Bergeron	Modeling Usable and Reusable Transactors in System Verilog.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Kaushal R. Gandhi, Nihar R. Mahapatra	Dynamically Exploiting Frequent Operand Values for Energy Efficiency in Integer Functional Units.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar	A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Integrated On-Chip Storage Evaluation in ASIP Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey	A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC.	VLSI Design	2005	DBLP DOI BibTeX RDF	MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power
41	Shubhajit Roy Chowdhury, C. Pramanik, Hiranmay Saha	ASIC Design of the Linearisation Circuit of a PTC Thermistor.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	D. Mukhopadhyay, P. K. Basu, V. Ramgopal Rao	Physics and Technology: Towards Low-Power DSM Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim 0001, Thomas Chen	A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Atul Katoch, Maurice Meijer, Sanjeev K. Jain	Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication.	VLSI Design	2005	DBLP DOI BibTeX RDF
41	Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran	Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.	VLSI Design	2005	DBLP DOI BibTeX RDF