Search results for "Verilog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
105	Jennifer Gillenwater, Gregory Malecha, Cherif R. Salama, Angela Yun Zhu, Walid Taha, Jim Grundy, John O'Leary	Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability.	PEPM	2008	DBLP DOI BibTeX RDF	statically typed two-level languages, synthesizability, verilog elaboration, code generation, hardware description languages
103	Cherif R. Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary	Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions.	PEPM	2009	DBLP DOI BibTeX RDF	static array bounds checking, verilog elaboration, verilog wire width consistency, dependent types, dead code elimination
76	Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang	Hardware/Software Partitioning in Verilog.	ICFEM	2002	DBLP DOI BibTeX RDF
76	Ravi Surepeddi	System Verilog for Quality of Results (QoR).	ISQED	2008	DBLP DOI BibTeX RDF	System Verilog Design Quality Results
76	Shengchao Qin, Wei-Ngan Chin, Jifeng He 0001, Zongyan Qiu	From Statecharts to Verilog: a formal approach to hardware/software co-specification.	Innov. Syst. Softw. Eng.	2006	DBLP DOI BibTeX RDF	Operational semantics, Statecharts, Hardware/software partitioning, Homomorphism, Verilog, Algebraic laws
66	David R. Smith	Hardware Synthesis From Encapsulated Verilog Modules.	ASAP	1996	DBLP DOI BibTeX RDF	encapsulated Verilog modules, Verilog writing style, code complexity, automatic inference of control, low level simulation, computational complexity, logic design, inference mechanisms, hardware description languages, hardware synthesis, control points, clock cycle
58	Youngsun Han, Seon Kim, Chulwoo Kim	Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing.	ICESS	2005	DBLP DOI BibTeX RDF	Java, FPGA, compiler, Reconfigurable computing, Verilog
57	Lijun Li, Carl Tropper	A Multiway Partitioning Algorithm for Parallel Gate Level Verilog Simulation.	ICPP	2008	DBLP DOI BibTeX RDF
57	François Pêcheux, Christophe Lallement, Alain Vachoux	VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
56	Huibiao Zhu, Jifeng He 0001, Jonathan P. Bowen	From algebraic semantics to denotational semantics for Verilog.	Innov. Syst. Softw. Eng.	2008	DBLP DOI BibTeX RDF	Unifying theories of programming, Denotational semantics, Semantic relating, Verilog, Algebraic semantics
56	Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau	Understanding bug fix patterns in verilog.	MSR	2008	DBLP DOI BibTeX RDF	error classification, VHDL, verilog
56	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word level predicate abstraction and refinement for verifying RTL verilog.	DAC	2005	DBLP DOI BibTeX RDF	SAT, predicate abstraction, verilog
56	Shengchao Qin, Wei-Ngan Chin	Mapping Statecharts to Verilog for Hardware/Software Co-specification.	FME	2003	DBLP DOI BibTeX RDF	operational semantics, Statecharts, homomorphism, Verilog
56	Arash Saifhashemi, Hossein Pedram	Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.	DAC	2003	DBLP DOI BibTeX RDF	CHP, PLI, CSP, asynchronous circuits, channel, verilog
48	Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen	VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.	ISQED	2009	DBLP DOI BibTeX RDF
47	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
47	Bernhard Peischl, Naveed Riaz, Franz Wotawa	Advances in Automated Source-Level Debugging of Verilog Designs.	New Challenges in Applied Intelligence Technologies	2008	DBLP DOI BibTeX RDF	debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging
47	Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin	An Automatic Mapping from Statecharts to Verilog.	ICTAC	2004	DBLP DOI BibTeX RDF
47	Daniel Kroening, Edmund M. Clarke	Checking consistency of C and Verilog using predicate abstraction and induction.	ICCAD	2004	DBLP DOI BibTeX RDF
47	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems.	ISPDC	2003	DBLP DOI BibTeX RDF
47	Yongjian Li, Jifeng He 0001	Towards a Theory of Bisimulation for a Fragment of Verilog.	IPDPS	2003	DBLP DOI BibTeX RDF
47	Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001	From Operational Semantics to Denotational Semantics for Verilog.	CHARME	2001	DBLP DOI BibTeX RDF
47	David J. Greaves	A Verilog to C Compiler.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
47	James Jennings, Eric Beuscher	Verischemelog: Verilog embedded in Scheme.	DSL	1999	DBLP DOI BibTeX RDF
47	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
47	Ulya R. Karpuzcu	Automatic verilog code generation through grammatical evolution.	GECCO Workshops	2005	DBLP DOI BibTeX RDF	automatic code generation, grammatical evolution, verilog
47	Zaher S. Andraus, Karem A. Sakallah	Automatic abstraction and verification of verilog models.	DAC	2004	DBLP DOI BibTeX RDF	UCLID, logic of counter arithmetic with lambda expressions and uninter-preted functions (CLU), abstraction, register transfer level (RTL), verilog
39	Karl Meier, Alessandro Forin	Hardware Compilation from Machine Code with M2V.	FCCM	2008	DBLP DOI BibTeX RDF
39	Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull	Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.	DATE	2007	DBLP DOI BibTeX RDF
39	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
38	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
38	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
38	Clifford E. Cummings	SystemVerilog implicit port enhancements accelerate system design & verification.	DAC	2008	DBLP DOI BibTeX RDF	*, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog
37	Ondrej Subrt, Petr Struhovský, Pravoslav Martínek, Jirí Hospodka	Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.	DDECS	2008	DBLP DOI BibTeX RDF
37	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
37	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
37	Lijun Li, Carl Tropper	A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation.	PADS	2007	DBLP DOI BibTeX RDF
37	Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P. Chakrabarti 0001	Synthesis of system verilog assertions.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
37	Huibiao Zhu, Jifeng He 0001, Jonathan P. Bowen	From Algebraic Semantics to Denotational Semantics for Verilog.	ICECCS	2006	DBLP DOI BibTeX RDF
37	Rishiyur S. Nikhil	Bluespec System Verilog: efficient, correct RTL from high level specifications.	MEMOCODE	2004	DBLP DOI BibTeX RDF
37	Tom Fitzpatric	System Verilog for VHDL Users.	DATE	2004	DBLP DOI BibTeX RDF
37	Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev	An Asynchronous Synthesis Toolset Using Verilog.	DATE	2004	DBLP DOI BibTeX RDF
37	Tun Li, Yang Guo 0003, Sikun Li, Fujiang Ao, Gongjie Li	Parallel verilog simulation: architecture and circuit partition.	ASP-DAC	2004	DBLP DOI BibTeX RDF
37	Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo	A Temporal Assertion Extension to Verilog.	ATVA	2004	DBLP DOI BibTeX RDF	temporal assertion, verification, PSL
37	Tun Li, Yang Guo 0003, Sikun Li	Design and Implementation of a Parallel Verilog Simulator: PVSim.	VLSI Design	2004	DBLP DOI BibTeX RDF
37	Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001	Soundness, Completeness and Non-redundancy of Operational Semantics for Verilog Based on Denotational Semantics.	ICFEM	2002	DBLP DOI BibTeX RDF
37	Jifeng He 0001	An Algebraic Approach to the VERILOG Programming.	10th Anniversary Colloquium of UNU/IIST	2002	DBLP DOI BibTeX RDF
37	Kartik Mohanram, C. V. Krishna, Nur A. Touba	A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
37	Huibiao Zhu, Jonathan P. Bowen, Jifeng He 0001	Deriving Operational Semantics from Denotational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
37	Jordan Dimitrov	Operational Semantics for Verilog.	APSEC	2001	DBLP DOI BibTeX RDF
37	Ivan Blunno, Luciano Lavagno	Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL.	ASYNC	2000	DBLP DOI BibTeX RDF
37	Gerardo Schneider, Qiwen Xu	Towards a Formal Semantics of Verilog Using Duration Calculus.	FTRTFT	1998	DBLP DOI BibTeX RDF
37	Edmund M. Clarke, Daniel Kroening, Karen Yorav	Behavioral consistency of C and verilog programs using bounded model checking.	DAC	2003	DBLP DOI BibTeX RDF	ANSI-C, equivalence checking, verilog
36	Qinlin Chen, Nairen Zhang, Jinpeng Wang, Tian Tan 0001, Chang Xu 0001, Xiaoxing Ma, Yue Li 0006	The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog.	Proc. ACM Program. Lang.	2023	DBLP DOI BibTeX RDF
36	Yicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao 0004, Wei Mao, Yongfu Li 0002	V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation.	APCCAS	2023	DBLP DOI BibTeX RDF
36	Moon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim	Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
36	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
36	Cherif R. Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O'Leary	Static consistency checking for Verilog wire interconnects - Using dependent types to check the sanity of Verilog descriptions.	High. Order Symb. Comput.	2011	DBLP DOI BibTeX RDF
36	Mile K. Stojcev	S. Sutherland, S. Davidman and P. Flake, System Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling Hardcover, Kluwer Academic Publishers, Norwell, MA (2004) ISBN 1-4020-7530-8 pp 374, plus XXVIII, euro 119.	Microelectron. Reliab.	2006	DBLP DOI BibTeX RDF
36	Douglas J. Smith	VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C.	DAC	1996	DBLP DOI BibTeX RDF	VHDL
29	Johannes Jendrsczok, Rolf Hoffmann, Thomas Lenck	Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation.	ARCS	2009	DBLP DOI BibTeX RDF
29	John A. Nestor	Teaching Computer Organization with HDLs: An Incremental Approach.	MSE	2005	DBLP DOI BibTeX RDF
29	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.	DFT	2005	DBLP DOI BibTeX RDF
29	Lin Yuan, Pushkin R. Pari, Gang Qu 0001	Soft IP Protection: Watermarking HDL Codes.	Information Hiding	2004	DBLP DOI BibTeX RDF
29	Dennis Abts, Steve Scott, David J. Lilja	So Many States, So Little Time: Verifying Memory Coherence in the Cray X1.	IPDPS	2003	DBLP DOI BibTeX RDF
29	Siavash Bayat Sarmadi, Seyed Ghassem Miremadi, Ghazanfar Asadi, Ali Reza Ejlali	Fast Prototyping with Co-operation of Simulation and Emulation.	FPL	2002	DBLP DOI BibTeX RDF
29	Guido Arnout	C for System Level Design.	DATE	1999	DBLP DOI BibTeX RDF
29	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
29	Gaurav Singh 0006, Sandeep K. Shukla	Verifying Compiler Based Refinement of BluespecTM.	SPIN	2008	DBLP DOI BibTeX RDF	Bluespec System Verilog (BSV), Formal Verification, Hardware Designs, SPIN Model Checker
29	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	Int. J. Softw. Tools Technol. Transf.	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
29	Li Shen 0002	VFSim: Concurrent Fault Simulation at Register Transfer Level.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, Verilog, high-level testing, circuit modeling
29	Choudhury A. Rahman, Wael M. Badawy	A quarter pel full search block motion estimation architecture for H.264/AVC.	ICME	2005	DBLP DOI BibTeX RDF	CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
29	Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee	PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations.	CASES	2002	DBLP DOI BibTeX RDF	FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization
29	M. E. Waite, T. J. Reynolds, F. Z. Ieromnimon	Parallel Graph Reduction with the PACE Architecture.	PDP	1996	DBLP DOI BibTeX RDF	parallel graph reduction, PACE architecture, graph reduction model, basic replicable node, prototype version, Verilog description, C simulator, parallel programming, graph theory, parallel architectures, virtual machines, distributed memory systems, parallel execution, distributed memory multiprocessor
29	Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design.	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
29	Nam Ling, Rajesh Advani	Architecture of a fast motion estimator for MPEG video coding.	ISPAN	1996	DBLP DOI BibTeX RDF	fast motion estimator, MPEG video coding, 2-D log search, MPEG2 video, motion estimation, motion estimator, video coding, systolic arrays, motion vector, Verilog, Synopsys
29	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
28	Matthias Raffelsieper, Mohammad Reza Mousavi 0001, Jan-Willem Roorda, Chris W. H. Strolenberg, Hans Zantema	Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models.	FMICS	2009	DBLP DOI BibTeX RDF
28	Christian Haufe, Frank Rogin	Ad-Hoc Translations to Close Verilog Semantics Gap.	DDECS	2008	DBLP DOI BibTeX RDF
28	Flavius Gruian, Mark Westmijze	VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture.	SAC	2008	DBLP DOI BibTeX RDF	embedded systems, java processor, Bluespec
28	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	VCEGAR: Verilog CounterExample Guided Abstraction Refinement.	TACAS	2007	DBLP DOI BibTeX RDF
28	Junjun Li, Sopan Joshi, Ryan Barnes, Elyse Rosenbaum	Compact modeling of on-chip ESD protection devices using Verilog-A.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Ming-Ta Hsieh, Gerald E. Sobelman	Modeling and verification of high-speed wired links with Verilog-AMS.	ISCAS	2006	DBLP DOI BibTeX RDF
28	Tun Li, Yang Guo 0003, Sikun Li, GongJie Liu	Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming.	ATVA	2005	DBLP DOI BibTeX RDF
28	Tun Li, Yang Guo 0003, Sikun Li, Dan Zhu	Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions.	MICAI	2005	DBLP DOI BibTeX RDF
28	Jun Wang, Carl Tropper	Nicarus: A Distributed Verilog Compiler.	ICPP Workshops	2004	DBLP DOI BibTeX RDF
28	Lijun Li, Hai Huang, Carl Tropper	DVS: An Object-Oriented Framework for Distributed Verilog Simulation.	PADS	2003	DBLP DOI BibTeX RDF
28	Monte Mar, Bert Sullam	Modeling and verification of a programmable mixed-signal device using Verilog.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
28	Jonathan P. Bowen, Jifeng He 0001, Qiwen Xu	An Animatable Operational Semantics of the Verilog Hardware Description Language.	ICFEM	2000	DBLP DOI BibTeX RDF
28	Alexander Glasmacher, Kai Woska	Design and Implementation of an XC6216 FPGA Model in Verilog.	FPL	2000	DBLP DOI BibTeX RDF
28	Jonathan P. Bowen	Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language.	IFM	2000	DBLP DOI BibTeX RDF
28	Gordon J. Pace	The Semantics of Verilog Using Transition System Combinators.	FMCAD	2000	DBLP DOI BibTeX RDF
28	Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT.	DAC	1997	DBLP DOI BibTeX RDF
28	Dominique Borrione, Robert Piloty, Dwight D. Hill, Karl J. Lieberherr, Philip Moorby	Three Decades of HDLs: Part II, Conlan Through Verilog.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
19	Shreesha Srinath, Katherine Compton	Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks.	FPGA	2010	DBLP DOI BibTeX RDF	asymmetric multipliers, composable multipliers, multiplier design
19	Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough	Instrumenting AMS assertion verification on commercial platforms.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
19	Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil	Automatic Constraint Based Test Generation for Behavioral HDL Models.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
19	Jonathan Bachrach, Dany Qumsiyeh, Mark M. Tobenkin	Hardware Scripting in Gel.	FCCM	2008	DBLP DOI BibTeX RDF
19	Pao-Lung Chen	Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Sangeetha Sudhakrishnan, Liying Su, Jose Renau	Processor Verification with hwBugHunt.	ISQED	2008	DBLP DOI BibTeX RDF