Search results for "Verilog-AMS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
191	François Pêcheux, Christophe Lallement, Alain Vachoux	VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
77	Sri Chandra	Driving Analog Mixed Signal Verification through Verilog-AMS.	VLSI Design	2008	DBLP DOI BibTeX RDF
71	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
56	Ming-Ta Hsieh, Gerald E. Sobelman	Modeling and verification of high-speed wired links with Verilog-AMS.	ISCAS	2006	DBLP DOI BibTeX RDF
53	B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001	Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development.	SCSC	2007	DBLP BibTeX RDF	smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS
35	Francesco Tosoni 0002, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi	A Framework for Modeling and Concurrently Simulating Mechanical and Electrical Faults in Verilog-AMS.	FDL	2022	DBLP DOI BibTeX RDF
35	Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi	Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models.	ISQED	2022	DBLP DOI BibTeX RDF
35	Nicola Dall'Ora, Enrico Fraccaroli, Sara Vinco, Franco Fummi	Multi-Discipline Fault Modeling with Verilog-AMS.	ICPS	2021	DBLP DOI BibTeX RDF
35	Nicola Dall'Ora, Sara Vinco, Franco Fummi	Functionality and Fault Modeling of a DC Motor with Verilog-AMS.	INDIN	2020	DBLP DOI BibTeX RDF
35	Bo Li 0056, Yonglei Zhao, Guoyong Shi	A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS.	Neurocomputing	2019	DBLP DOI BibTeX RDF
35	Saraju P. Mohanty, Elias Kougianos	iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization.	CoRR	2019	DBLP BibTeX RDF
35	David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez	VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC.	PATMOS	2018	DBLP DOI BibTeX RDF
35	Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz	System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS.	SMACD	2018	DBLP DOI BibTeX RDF
35	Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi	Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
35	Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi	Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS.	ICICDT	2017	DBLP DOI BibTeX RDF
35	Poorna Marthi, Nazir Hossain, Huan Wang 0009, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González	Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
35	Anders Jakobsson, Adriana Serban, Shaofang Gong	Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
35	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah	Polynomial Metamodel integrated Verilog-AMS for memristor-based mixed-signal system design.	MWSCAS	2013	DBLP DOI BibTeX RDF
35	Mahmoud Fawzy Wagdy, Sandesh Maraliga Jayaram	A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations.	ITNG	2013	DBLP DOI BibTeX RDF
35	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah	iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration.	ASAP	2013	DBLP DOI BibTeX RDF
35	Beatriz Blanco-Filgueira, Paula López 0001, Juan Bautista Roldán	A Verilog-AMS photodiode model including lateral effects.	Microelectron. J.	2012	DBLP DOI BibTeX RDF
35	Zhipeng Ye, Wenbin Chen, Michael Peter Kennedy	Modeling and Simulation of Delta-Sigma Fractional-N PLL Frequency Synthesizer in Verilog-AMS.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
35	Peter Frey, Donald O'Riordan	Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules.	BMAS	2000	DBLP DOI BibTeX RDF
32	Scott Little, Alper Sen 0001, Chris J. Myers	Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits.	MTV	2007	DBLP DOI BibTeX RDF
28	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
28	Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu	High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.	ISMVL	2008	DBLP DOI BibTeX RDF	Verilog-AMS, Static timing analysis, Look-up table
21	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
21	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu	An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
21	Monte Mar, Bert Sullam	Modeling and verification of a programmable mixed-signal device using Verilog.	ISCAS (3)	2003	DBLP DOI BibTeX RDF