Search results for "Wiring"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
130	Rosemary M. Francis, Simon W. Moore	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.	FPGA	2009	DBLP DOI BibTeX RDF	tdm wiring, fpga, routing
102	Katsunori Kitano, Tomoki Fukai	Variability v.s. synchronicity of neuronal activity in local cortical network models with different wiring topologies.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Neuronal wiring, Irregular firing, Computational model, Small-world network, Synchrony
85	J. T. Mowchenko, Y. Yang	Optimizing wiring space in slicing floorplans.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout
70	Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai	Interchangeable pin routing with application to package layout.	ICCAD	1996	DBLP DOI BibTeX RDF	BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems
65	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	BIST insertion, wiring area, simulated annealing, test synthesis
63	Rosemary M. Francis, Simon W. Moore, Robert D. Mullins	A Network of Time-Division Multiplexed Wiring for FPGAs.	NOCS	2008	DBLP DOI BibTeX RDF	time division multplexing, fpga, network-on-chip
63	Steven L. Teig	The X architecture: not your father's diagonal wiring.	SLIP	2002	DBLP DOI BibTeX RDF
63	Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III	Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.	DATE	1998	DBLP DOI BibTeX RDF	signature-invariance, circuit mutants, benchmarking, equivalence class
63	Thomas Lengauer, Rolf Müller	Robust and accurate hierarchical floorplanning with integrated global wiring.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
58	Inder S. Gopal, Don Coppersmith, C. K. Wong	Optimal Wiring of Movable Terminals.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	wiring channels, movable terminals, VLSI chip design, dynamic programming, optimal algorithms, Analysis of algorithms, NP-complete problems, wiring, vias
57	Jae-dong Lee, Kenneth E. Batcher	A bitonic sorting network with simpler flip interconnections.	ISPAN	1996	DBLP DOI BibTeX RDF	flip interconnections, bitonic sorting network, inter-level wiring, parity technique, Construct-BSMF, N/2 even-parity keys, interconnection scheme, perfect-shuffle interconnection, parallel algorithms, parallel architectures, multiprocessor interconnection networks, sorting
54	Chin Ngai Sze, Yu-Liang Wu	Improved alternative wiring scheme applying dominator relationship.	ASP-DAC	2001	DBLP DOI BibTeX RDF
54	Ioannis G. Tollis	A new approach to wiring layouts.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
48	Beth L. Chen, Dmitri B. Chklovskii	Placement and routing optimization in the brain.	ISPD	2006	DBLP DOI BibTeX RDF	wiring length minimization, linear programming, neurons, synapses, C. elegans
47	Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato	Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity.	PDP	2008	DBLP DOI BibTeX RDF	SDM, Spatial Division Multiplexing, parallel links, Networks on chip, NoCs, Wiring, Wires
47	Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl	Robust wiring networks for DfY considering timing constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	redundant wiring, timing constraint aware, open defects, design for yield
47	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.	DSD	2004	DBLP DOI BibTeX RDF	BIST insertion, wiring area, test synthesis
47	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	interconnect, multiple faults, adaptive diagnosis, Wiring network
47	Yu-Liang Wu, Wangning Long, Hongbing Fan	A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.	VLSI Design	2000	DBLP DOI BibTeX RDF	Alternative wiring, Graph-based pattern matching, Logic synthesis
47	Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi	Two-Step Algorithms for Maximal Diagnosis of Wiring Interconnects.	FTCS	1999	DBLP DOI BibTeX RDF	Interconnect, Multiple Faults, Adaptive Diagnosis, Wiring Network
47	Jeffrey Z. Su, Wayne Wei-Ming Dai	Post-route optimization for improved yield using a rubber-band wiring model.	ICCAD	1997	DBLP DOI BibTeX RDF	Rubber-Band, Topological Wiring Even Wire Distribution, Yield, Design for Manufacturability, Spacing, Bridge Fault, Routability, Critical Area, Layout Optimization, Routing Congestion
46	André DeHon	Rent's rule based switching requirements.	SLIP	2001	DBLP DOI BibTeX RDF	switching requirements, hierarchical networks, Rent's rule
46	Fran Hancheck, Shantanu Dutt	Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.	ICCD	1996	DBLP DOI BibTeX RDF
46	Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, John Moll	A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect.	ICCD	1996	DBLP DOI BibTeX RDF
45	Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002	Yield Improvement by Local Wiring Redundancy.	ISQED	2006	DBLP DOI BibTeX RDF
45	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead.	DELTA	2004	DBLP DOI BibTeX RDF
45	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
45	Wing K. Luk, Donald T. Tang, C. K. Wong	Hierarchial global wiring for custom chip design.	DAC	1986	DBLP DOI BibTeX RDF
40	Hungwen Li, Massimo Maresca	Polymorphic-Torus Network.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	polymorphic-torus network, parallel fine-grained, circuit-switching capability, wiring complexity, interpackage wiring, max/min, sum operations, interconnection network, multiprocessor interconnection networks, SIMD, communication bandwidth, Boolean
39	Jun-nosuke Teramae, Tomoki Fukai	Local cortical circuit model inferred from power-law distributed neuronal avalanches.	J. Comput. Neurosci.	2007	DBLP DOI BibTeX RDF	Neuronal wiring, Cortical network development, Synchronization, Synfire chain, Cell assembly
38	Martin L. Brady, Majid Sarrafzadeh	Stretching a Knock-Knee Layout for Multilayer Wiring.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	knock-knee layout stretching, multilayer wiring, knock-knee mode, 4/3 approximation algorithm, VLSI, VLSI, NP-complete, optimal algorithm, circuit layout CAD
37	Martijn T. Bennebroek	Validation of wire length distribution models on commercial designs.	SLIP	2003	DBLP DOI BibTeX RDF
37	Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie	Wire layer geometry optimization using stochastic wire sampling.	SLIP	2002	DBLP DOI BibTeX RDF	genetic algorithms, optimization, interconnect, Rent's rule
37	D. B. Polkl	A Three-Layer Gridless Channel Router with Compaction.	DAC	1987	DBLP DOI BibTeX RDF
36	Yunkyu Sohn, Jaeseung Jeong	Inferring Behavioral-level Circuits of Caenorhabditis elegans from the Topology of its Wiring Diagram.	BIBE	2007	DBLP DOI BibTeX RDF
36	Fei He 0001, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu 0001, Jia-Guang Sun 0001	A Hierachical Method for Wiring and Congestion Prediction.	ISVLSI	2005	DBLP DOI BibTeX RDF
36	Dmitri B. Chklovskii	Evolution as the blind engineer: wiring minimization in the brain.	SLIP	2004	DBLP DOI BibTeX RDF
36	Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda	Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond.	ICCD	2000	DBLP DOI BibTeX RDF
36	Rony Kay, Lawrence T. Pileggi	EWA: efficient wiring-sizing algorithm for signal nets and clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
36	Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu	Optimal diagnostic methods for wiring interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
36	Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner 0001, Karsten Weihe	Wiring Knock-Knee Layouts: A Global Appoach.	ISAAC	1992	DBLP DOI BibTeX RDF
35	Cher Ming Tan, Kim Peng Lim, Tai Chong Chai, Guat Cheng Lim	Non-destructive identification of open circuit in wiring on organic substrate with high wiring density covered with solder resist.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
29	Norio Kuji, Takako Ishihara	EB-Testing-Pad Method and Its Evaluation by Actual Devices.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability
29	Bin Liu, Fabrizio Lombardi, Wei-Kang Huang	Testing programmable interconnect systems: an algorithmic approach.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
29	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
29	Jacob Savir	On shrinking wide compressors.	VTS	1995	DBLP DOI BibTeX RDF	wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
28	Jun Nishiyama, Hiroyuki Sugahara, Tetsuya Okada, Takashi Kunifuji, Yamato Fukuta, Masayuki Matsumoto	A signal control system by optical LAN and design simplification.	SMC	2007	DBLP DOI BibTeX RDF
28	Zhuo Li 0001, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi	Probabilistic Congestion Prediction with Partial Blockages.	ISQED	2007	DBLP DOI BibTeX RDF
28	Devang Jariwala, John Lillis	Trunk decomposition based global routing optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
28	Hiroyuki Sugahara, Takashi Kunifuji, Tetsunori Hattori, Yoshiyuki Hirano, Yamato Fukuta, Masayuki Matsumoto	Assurance Technologies for Signal Control System by Optical LAN.	ICDCS Workshops	2006	DBLP DOI BibTeX RDF	Signal control system, E-PON, Field Controller, Optical LAN, Logical Controller
28	André DeHon, Raphael Rubin	Design of FPGA interconnect for multilevel metallization.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
28	Davide Pandini, Cristiano Forzan, Livio Baldi	Design Methodologies and Architecture Solutions for High-Performance Interconnects.	ICCD	2004	DBLP DOI BibTeX RDF
28	Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright	Prediction of interconnect pattern density distribution: derivation, validation, and applications.	SLIP	2003	DBLP DOI BibTeX RDF	interconnect network prediction, interconnect pattern density, Stochastic model, probability density function
28	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Congestion-Aware Logic Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
28	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
28	Kenneth Rose	A comprehensive look at system level model.	SLIP	2001	DBLP DOI BibTeX RDF
28	David Staepelaere, Jeffrey Jue, Tal Dayan, Wayne Wei-Ming Dai	SURF: Rubber-Band Routing System for Multichip Modules.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
28	Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot	Multilevel Synthesis Minimizing the Routing Factor.	DAC	1990	DBLP DOI BibTeX RDF
28	J. Fernando Naveda, K. C. Chang 0001, David Hung-Chang Du	A new approach to multi-layer PCB routing with short vias.	DAC	1986	DBLP DOI BibTeX RDF
28	Michael Burstein, Mary N. Youssef	Timing influenced layout design.	DAC	1985	DBLP DOI BibTeX RDF
27	Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang	Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles.	ISPD	2010	DBLP DOI BibTeX RDF	routing, linear programming, network flow, electromigration
27	Claudius Gläser, Frank Joublin, Christian Goerick	Enhancing Topology Preservation during Neural Field Development Via Wiring Length Minimization.	ICANN (1)	2008	DBLP DOI BibTeX RDF
27	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0.	MICRO	2007	DBLP DOI BibTeX RDF	non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
27	Dirk Niebuhr, Andreas Rausch	A concept for dynamic wiring of components: correctness in dynamic adaptive systems.	SAVCBS	2007	DBLP DOI BibTeX RDF	runtime testing, adaptation, component, reconfiguration, correctness, dynamic adaptive systems
27	Marc Benkert, Martin Nöllenburg, Takeaki Uno, Alexander Wolff 0001	Minimizing Intra-edge Crossings in Wiring Diagrams and Public Transportation Maps.	GD	2006	DBLP DOI BibTeX RDF
27	Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen	Wiring area optimization in floorplan-aware hierarchical power grids.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
27	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.	ISQED	2004	DBLP DOI BibTeX RDF
27	Lawrence S. Baum, John H. Boose, Molly L. Boose, Carey Chaplin, Ron Provine	Extracting System-Level Understanding from Wiring Diagram Manuals.	GREC	2003	DBLP DOI BibTeX RDF
27	Satoshi Tayu, Mineo Kaneko	Characterization and computation of Steiner wiring based on Elmore's delay model.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
27	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita	Chip size estimation based on wiring area.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
27	Heidi M. E. Korhonen, Jussi Heikkilä 0002, Jon M. Törnwall	A simulation case study of production planning and control in printed wiring board manufacturing.	WSC	2001	DBLP DOI BibTeX RDF
27	Jun Dong Cho	Wiring space and length estimation in two-dimensional arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
27	Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai	An Even Wiring Approach to the Ball Grid Array Package Routing.	ICCD	1999	DBLP DOI BibTeX RDF
27	Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen	NEWS: a net-even-wiring system for the routing on a multilayer PGA package.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
27	Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto	QFP wiring problem-introduction and analytical considerations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
27	Kuo-En Chang	Efficient algorithms of wiring channels with movable terminals.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	C. C. Martin, K. K. Hutchison	Computer aided concurrent design for printed wiring boards.	IEA/AIE (1)	1989	DBLP DOI BibTeX RDF	Prolog
27	Gotaro Odawara, T. Hamuro, Kazuhiko Iijima, T. Yoshino, Y. Dai	A Rule-Based Placement System for Printed Wiring Boards.	DAC	1987	DBLP DOI BibTeX RDF
27	Toshihiko Tada, Akihiko Hanafusa	Router system for printed wiring boards of very high-speed, very large-scale computers.	DAC	1986	DBLP DOI BibTeX RDF
27	Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi	Knowledge-based placement technique for printed wiring boards.	DAC	1985	DBLP DOI BibTeX RDF
20	Aimee Rydarowski, Özge Samanci, Ali Mazalek	Murmur: kinetic relief sculpture, multi-sensory display, listening machine.	TEI	2008	DBLP DOI BibTeX RDF	CPU fan, mechatronic art, multi-sensory displays, information visualization, interactive art, ambient displays, wiring
20	Jing Li, Tan Yan, Bo Yang 0011, Juebang Yu, Chunhui Li	A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation.	DAC	2004	DBLP DOI BibTeX RDF	O-tree representation, VLSI circuit physical design, Y- architecture, diagonal wiring, non-Manhattan layout, placement
20	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Adaptive Fault Detection and Diagnosis of RAM Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, memory, diagnosis, detection, wiring
20	Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro	Improved Selay Prediction for On-Chip Buses.	DAC	1999	DBLP DOI BibTeX RDF	RC wiring delay, buffer optimization, high-level synthesis, floorplanning, interconnect optimization
20	Fran Hanchek, Shantanu Dutt	Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	cell faults, wiring faults, Fault tolerance, Field Programmable Gate Array (FPGA), reconfiguration, yield improvement
20	Man-Fai Yu, Wayne Wei-Ming Dai	Single-layer fanout routing and routability analysis for Ball Grid Arrays.	ICCAD	1995	DBLP DOI BibTeX RDF	package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
20	Franco P. Preparata, Witold Lipski Jr.	Optimal Three-Layer Channel Routing.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	multilayer wiring, VLSI design, optimal algorithms, VLSI layouts, Channel routing
18	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).	FPGA	2010	DBLP DOI BibTeX RDF	structured asics, via programmable fabric
18	Ling Zhang, Yulei Zhang 0002, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng	High performance on-chip differential signaling using passive compensation for global communication.	ASP-DAC	2009	DBLP DOI BibTeX RDF
18	Kaustav Banerjee	Graphene based nanomaterials for VLSI interconnect and energy-storage applications.	SLIP	2009	DBLP DOI BibTeX RDF	carbon nanomaterials, graphene nano-ribbons, interconnects, carbon nanotubes, passives
18	Tilo Meister, Jens Lienig, Gisbert Thomke	Novel Pin Assignment Algorithms for Components with Very High Pin Counts.	DATE	2008	DBLP DOI BibTeX RDF
18	Shannon Koh, Oliver Diessel	The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration.	FCCM	2008	DBLP DOI BibTeX RDF
18	Dmitri "Mitya" Chklovskii	What can brain researchers learn from computer engineers and vice versa?	ICCAD	2008	DBLP DOI BibTeX RDF
18	Yulei Zhang 0002, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng	On-chip high performance signaling using passive compensation.	ICCD	2008	DBLP DOI BibTeX RDF
18	Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl	IntSim: A CAD tool for optimization of multilevel interconnect networks.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang	ECO timing optimization using spare cells.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan	On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.	DAC	2007	DBLP DOI BibTeX RDF
18	Rod Adams, Lee Calcraft, Neil Davey	Evolved Patterns of Connectivity in Associative Memory Models.	IEEE ICCI	2006	DBLP DOI BibTeX RDF
18	Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das	ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.	MICRO	2006	DBLP DOI BibTeX RDF
18	Mario Chauca, Juan C. Seminario Castro, Walter Flores Matias, Eder Pacheco Aaron	Control System Over Power Line.	CONIELECOMP	2006	DBLP DOI BibTeX RDF	optocoupler, demodulation, power line, modulation