Search results for "accelerator"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
92	Like Yan, Gang Wang, Tianzhou Chen	The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.	FPGA	2009	DBLP DOI BibTeX RDF	dynamic adaption, reconfigurable system, loop unrolling, loop accelerator
84	Gokhan Memik, Seda Ogrenci Memik, William H. Mangione-Smith	Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic.	FCCM	2002	DBLP DOI BibTeX RDF
84	Michael Cox, Narendra Bhandari, Michael Shantz	Multi-Level Texture Caching for 3D Graphics Hardware.	ISCA	1998	DBLP DOI BibTeX RDF
82	Gokhan Memik, William H. Mangione-Smith	A flexible accelerator for layer 7 networking applications.	DAC	2002	DBLP DOI BibTeX RDF	pattern matching, network processor, accelerator, table lookup, application-specific processor, networking applications
75	Jungmin Lee, Zhiling Lan, James F. Amundson, Panagiotis Spentzouris	Evaluating Performance and Scalability of Advanced Accelerator Simulations.	CCGRID	2006	DBLP DOI BibTeX RDF
66	Satnam Singh	Declarative data-parallel programming with the accelerator system.	DAMP	2010	DBLP DOI BibTeX RDF	data-parallelsim
65	Jae-Gon Lee, Chong-Min Kyung	PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
64	Junho Ahn, Jung-Hi Min, Hojung Cha, Rhan Ha	A Power Management mechanism for Handheld Systems having a Multimedia Accelerator.	PerCom	2008	DBLP DOI BibTeX RDF	handheld systems, multimedia accelerator, power management, CPU
61	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Partitioning Programming Environment for a Novel Parallel Architecture.	IPPS	1996	DBLP DOI BibTeX RDF	partitioning programming environment, novel parallel architecture, embedded accelerator, reconfigurable datapath hardware, accelerator partitioning, profiling-driven partitioning, resource-driven sequential partitioning, resource-driven structural partitioning, parallel architectures, software tools, programming environments, reconfigurable architectures, software performance evaluation, parallelizing compiler, performance optimization, program interpreters, parallelising compilers, parallelizing programming environment, optimising compilers, C programs
56	Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami	Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator.	ICESS	2007	DBLP DOI BibTeX RDF
56	Robert D. Ryne	High energy physics - 25 years of accelerator modeling.	SC	2006	DBLP DOI BibTeX RDF
56	Catherine H. Crawford, Paul Henning, Michael Kistler, Cornell Wright	Accelerating computing with the cell broadband engine processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	hybrid programming models, accelerators
56	Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee 0006, Chong-Min Kyung	A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation.	DATE	2005	DBLP DOI BibTeX RDF
55	Zhili Zhang, Ling Zhang, Dang-en Xie, Hongchao Xu, Haina Hu	A Novel DNS Accelerator Design and Implementation.	APNOMS	2009	DBLP DOI BibTeX RDF	Renewal policy, Accelerator, DNS, TTL
52	Reiner W. Hartenstein, Jürgen Becker 0001	Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators.	VLSI Design	1997	DBLP DOI BibTeX RDF	data-driven Xputer-based accelerators, CoDe-X, profiling-driven host/accelerator partitioning, resource-driven sequential/structural partitioning, accelerator source code, reconfigurable resources, C dialect, data-procedural language features, parallel programming, partitioning, performance optimization, hardware/software co-design, parallelizing programming environment
52	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
47	Gang Wang, Du Chen, Jian Chen, Jianliang Ma, Tianzhou Chen	A Performance Model for Run-Time Reconfigurable Hardware Accelerator.	APPT	2009	DBLP DOI BibTeX RDF
47	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	Designing an Efficient Hardware Implication Accelerator for SAT Solving.	SAT	2008	DBLP DOI BibTeX RDF
47	Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton	Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.	ISVLSI	2005	DBLP DOI BibTeX RDF
47	Cyprian Grassmann, Joachim K. Anlauf	RACER - A Rapid Prototyping Accelerator for Pulsed Neural Networks.	FCCM	2002	DBLP DOI BibTeX RDF
47	Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen	A hardware accelerator for video segmentation using programmable morphology PE array.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
47	Andrei Vladimirescu, David Weiss, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass	A Vector Hardware Accelerator with Circuit Simulation Emphasis.	DAC	1987	DBLP DOI BibTeX RDF
46	Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt	Efficient memory management for hardware accelerated Java Virtual Machines.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Java Virtual Machine, hardware acceleration, Dynamic memory management
46	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
46	Jeff H. Derby, Robert K. Montoye, José E. Moreira	VICTORIA: VMX indirect compute technology oriented towards in-line acceleration.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	VMX, SIMD, accelerators, powerPC
45	Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose	Performance and power evaluation of an in-line accelerator.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	vmx, accelerator, powerpc, simd
45	Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang 0004	Energy efficient architecture of sensor network node based on compression accelerator.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	compression accelerator, wireless sensor network, energy efficient, chip design
45	Manjunath Kudlur, Kevin Fan, Scott A. Mahlke	Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system-level synthesis, loop accelerator, application-specific hardware
45	Daniel Dietterle, Rolf Kraemer	A hardware accelerated implementation of the IEEE 802.15.3 MAC protocol.	Telecommun. Syst.	2009	DBLP DOI BibTeX RDF	Hardware accelerator, Personal area networks, Protocol implementation
45	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation
45	Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman	Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.	IPDPS	2003	DBLP DOI BibTeX RDF	distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware
38	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
38	Alan Kennedy, Xiaojun Wang 0001, Bin Liu 0001	Energy efficient packet classification hardware accelerator.	IPDPS	2008	DBLP DOI BibTeX RDF
38	Kimmo U. Järvinen, Jorma O. Skyttä	High-Speed Elliptic Curve Cryptography Accelerator for Koblitz Curves.	FCCM	2008	DBLP DOI BibTeX RDF
38	Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan	ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator.	FCCM	2008	DBLP DOI BibTeX RDF
38	Stamatis Vassiliadis, Filipa Duarte, Stephan Wong	A Load/Store Unit for a Memcpy Hardware Accelerator.	FPL	2007	DBLP DOI BibTeX RDF
38	Salem Fawaz Adra, Ian Griffin, Peter J. Fleming	An informed convergence accelerator for evolutionary multiobjective optimiser.	GECCO	2007	DBLP DOI BibTeX RDF	evolutionary multiobjective optimisation, convergence acceleration
38	David Tarditi, Sidd Puri, Jose Oglesby	Accelerator: using data parallelism to program GPUs for general-purpose uses.	ASPLOS	2006	DBLP DOI BibTeX RDF	graphics processing units, data parallelism, just-in time compilation
38	Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere	Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.	PDCAT	2006	DBLP DOI BibTeX RDF
38	Jayaprakash Pisharath, Alok N. Choudhary	Design of a Hardware Accelerator for Density Based Clustering Applications.	ASAP	2005	DBLP DOI BibTeX RDF
38	Valery Biryukov, Angelika Drees, Raymond Patrick Fliller III, Nikolay Malitsky, Dejan Trbojevic	Tracking Particles in Accelerator Optics with Crystal Elements.	International Conference on Computational Science (3)	2002	DBLP DOI BibTeX RDF
38	Kwan-Liu Ma, Gregory L. Schussman, Brett Wilson, Kwok Ko, Ji Qiang, Robert D. Ryne	Advanced visualization technology for terascale particle accelerator simulations.	SC	2002	DBLP DOI BibTeX RDF	field lines, hardware-assisted techniques, particle accelerators, perception, high-performance computing, volume rendering, texture mapping, scientific visualization, vector field visualization, time-varying data, point-based rendering, visual cues
38	Gerald Frank, Georg Hartmann, Axel Jahnke, Martin Schäfer	An accelerator for neural networks with pulse-coded model neurons.	IEEE Trans. Neural Networks	1999	DBLP DOI BibTeX RDF
38	Björn Bergsten, Michel Couprie, Rubén González-Rubio, Brigitte Kerhervé, Mikal Ziane	A Parallel Database Accelerator.	PARLE (1)	1989	DBLP DOI BibTeX RDF
37	Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu	An asymmetric distributed shared memory model for heterogeneous parallel systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	asymmetric distributed shared memory, data-centric programming models, heterogeneous systems
37	Maurice Keller, Andrew Byrne, William P. Marnane	Elliptic Curve Cryptography on FPGA for Low-Power Applications.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low-power, Cryptography, elliptic curves
37	Peter Bertels, Wim Heirman, Dirk Stroobandt	Strategies for dynamic memory allocation in hybrid architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	java, memory management, hardware acceleration
37	Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang 0003	EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.	PLDI	2007	DBLP DOI BibTeX RDF	GPU, openMP, heterogeneous multi-cores
37	Antonin Hermanek, Michal Kunes, Michal Kvasnicka	Using Reconfigurable HW for High Dimensional CAF Computation.	FPL	2006	DBLP DOI BibTeX RDF
37	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
36	Hyunchul Park 0001, Yongjun Park 0001, Scott A. Mahlke	Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.	MICRO	2009	DBLP DOI BibTeX RDF	programmable accelerator, virtualization, software pipelining
36	Mark Hempstead, Gu-Yeon Wei, David M. Brooks	An accelerator-based wireless sensor network processor in 130nm CMOS.	CASES	2009	DBLP DOI BibTeX RDF	accelerator-based, wireless sensor networks, ultra-low power
36	Michael J. Lyons 0003, David M. Brooks	The design of a bloom filter hardware accelerator for ultra low power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	wireless sensor network, hardware accelerator, bloom filter
36	Jean-Luc Beuchat, Jérémie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodríguez-Henríquez	Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers.	CHES	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, FPGA, elliptic curve, hardware accelerator, Tate pairing, finite field arithmetic, ? T pairing
36	John H. Kelm, Daniel R. Johnson, Matthew R. Johnson 0003, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Rigel: an architecture and scalable programming interface for a 1000-core accelerator.	ISCA	2009	DBLP DOI BibTeX RDF	low-level programming interface, computer architecture, accelerator
36	Mario Porrmann, Ulf Witkowski, Heiko Kalte, Ulrich Rückert 0001	Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.	PDP	2002	DBLP DOI BibTeX RDF	Kohonen, FPGA, Artificial Neural Networks, Self-organizing Map, Reconfigurable, RBF, Hardware Accelerator, Associative Memory
35	Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
35	Yong Dou, Fei Xia, Jingfei Jiang	Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA.	CASES	2009	DBLP DOI BibTeX RDF	SCFGS, reconfigurable algorithm accelerator, secondary structure prediction, FPGA, RNA
35	Sébastien Lafond, Johan Lilius	Interrupt Costs in Embedded System with Short Latency Hardware Accelerators.	ECBS	2008	DBLP DOI BibTeX RDF	Interrupt, Hardware accelerator
35	John H. Kelm, Steven S. Lumetta	HybridOS: runtime support for reconfigurable accelerators.	FPGA	2008	DBLP DOI BibTeX RDF	CPU/accelerator architecture, operating system, reconfigurable computing
35	Giray Kömürcü, Erkay Savas	An Efficient Hardware Implementation of the Tate Pairing in Characteristic Three.	ICONS	2008	DBLP DOI BibTeX RDF	Bilinear pairings, hardware accelerator, Tate Pairing, FPGA Implementation, Characteristic Three
35	Chen-Yong Cher, Michael Gschwind	Cell GC: using the cell synergistic processor as a garbage collection coprocessor.	VEE	2008	DBLP DOI BibTeX RDF	BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
35	Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke	Increasing hardware efficiency with multifunction loop accelerators.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware
35	Monther Aldwairi, Thomas M. Conte, Paul D. Franzon	Configurable string matching hardware for speeding up intrusion detection.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	snort accelerator, string matchin, intrusion detection
35	Harald Simmler, Holger Singpiel, Reinhard Männer	Real-Time Primer Design for DNA Chips.	IPDPS	2003	DBLP DOI BibTeX RDF	Primer design, High performance parallel architecture, FPGA, Hardware accelerator, HPC
35	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table.	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
28	Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux	Vector Processing as a Soft Processor Accelerator.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
28	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	Reconfigurable accelerator for WFS-based 3D-audio.	IPDPS	2009	DBLP DOI BibTeX RDF
28	Yahya Jan, Lech Józwiak	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.	ARC	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
28	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
28	Ioannis Psaras, Vassilis Tsaoussidis	AIRA: Additive Increase Rate Accelerator.	Networking	2008	DBLP DOI BibTeX RDF
28	Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami	Design space exploration for a coarse grain accelerator.	ASP-DAC	2008	DBLP DOI BibTeX RDF
28	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.	DAC	2008	DBLP DOI BibTeX RDF	BCP, FPGA, reconfigurable, SAT solver, co-processor
28	Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.	ISVLSI	2007	DBLP DOI BibTeX RDF
28	Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid	Two-level microprocessor-accelerator partitioning.	DATE	2007	DBLP DOI BibTeX RDF
28	John A. Nestor, Jeremy Lavine	L4: An FPGA-Based Accelerator for Detailed Maze Routing.	FPL	2007	DBLP DOI BibTeX RDF
28	Zdenek Pohl, Milan Tichý	RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.	FPL	2007	DBLP DOI BibTeX RDF
28	Zhihua Cui, Jianchao Zeng 0001, Guoji Sun	Using Accelerator Feedback to Improve Performance of Integral-Controller Particle Swarm Optimization.	IEEE ICCI	2006	DBLP DOI BibTeX RDF
28	Seung Wook Lee, Jong Tae Kim, Hongmoon Wang, Dae Jin Bae, Keon-Myung Lee, Jee-Hyung Lee, Jae Wook Jeon	Architecture of RETE Network Hardware Accelerator for Real-Time Context-Aware System.	KES (1)	2006	DBLP DOI BibTeX RDF
28	Wan-Yu Chen, Yu-Lin Chang, Hsu-Kuang Chiu, Shao-Yi Chien, Liang-Gee Chen	Real-Time Depth Image based Rendering Hardware Accelerator for Advanced Three Dimensional Television System.	ICME	2006	DBLP DOI BibTeX RDF
28	Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, Han-Chiang Chen	Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator.	LCN	2006	DBLP DOI BibTeX RDF
28	Zheng Liang, Juha Plosila, Lu Yan, Kaisa Sere	On-chip Debug for an Asynchronous Java Accelerator.	PDCAT	2005	DBLP DOI BibTeX RDF	Java, Debug, Embedded, Asynchronous, Co-design
28	Valery Sklyarov, Iouliia Skliarova, Arnaldo S. R. Oliveira, António de Brito Ferrari	A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors.	DSD	2003	DBLP DOI BibTeX RDF
28	Jiri Novotný, Otto Fucík, David Antos	Project of IPv6 Router with FPGA Hardware Accelerator.	FPL	2003	DBLP DOI BibTeX RDF	Liberouter, Virtex II, FPGA, IPv6, router
28	Sheng-Bo Xu, Lejla Batina	Efficient Implementation of Elliptic Curve Cryptosystems on an ARM7 with Hardware Accelerator.	ISC	2001	DBLP DOI BibTeX RDF
28	Donald L. Hung, Heng-Da Cheng, Savang Sengkhamyong	Design of a configurable accelerator for moment computation.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
28	Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi	Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.	FPL	2000	DBLP DOI BibTeX RDF
28	Bertil Schmidt	Design of a Parallel Accelerator for Volume Rendering.	Euro-Par	2000	DBLP DOI BibTeX RDF
28	L. Louis Zhang, Qiang Wang, David M. Lewis	Design of a VLIW Compute Accelerator on the Transmogrifier-2.	FCCM	2000	DBLP DOI BibTeX RDF
28	Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems	The spring scheduling coprocessor: a scheduling accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
28	David M. Lewis	A Programmable Hardware Accelerator for Compiled Electrical Simulation.	DAC	1988	DBLP BibTeX RDF
28	Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar	Architecture and Design of the MARS Hardware Accelerator.	DAC	1987	DBLP DOI BibTeX RDF
28	Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq	A Hardware Accelerator for Maze Routing.	DAC	1987	DBLP DOI BibTeX RDF
28	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Energy reduction with run-time partial reconfiguration (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, energy
28	Ningyi Xu, Xiongfei Cai, Rui Gao, Lei Zhang 0001, Feng-Hsiung Hsu	FPGA Acceleration of RankBoost in Web Search Engines.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, hardware acceleration
28	Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose	Scheduling dynamic parallelism on accelerators.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	cooperative scheduling, cell be
28	Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi	HW/SW co-design architecture exploration for VLSI maze routing.	CCECE	2009	DBLP DOI BibTeX RDF
28	Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton	Petascale computing with accelerators.	PPoPP	2009	DBLP DOI BibTeX RDF	hybrid programming models, accelerators
28	Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal	Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
28	Giovanni Danese, Francesco Leporati, Marco Bera, Mauro Giachero, Nelson Nazzicari, Alvaro Spelgatti	An Application Specific Processor for Montecarlo Simulations.	PDP	2007	DBLP DOI BibTeX RDF