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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 685 occurrences of 426 keywords
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Results
Found 3067 publication records. Showing 3067 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | Eric William Burger, Guido Dedene |
Economics of point accelleration. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
CAD Development Methodology, Economics of CAD Systems, Routing Accelerators, Total CAD Systems, Logic Synthesis, Simulation Accelerators |
90 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation |
80 | Amir Hormati, Nathan Clark, Scott A. Mahlke |
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Kevin Fan, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke |
Increasing hardware efficiency with multifunction loop accelerators. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware |
70 | Sébastien Lafond, Johan Lilius |
Interrupt Costs in Embedded System with Short Latency Hardware Accelerators. |
ECBS |
2008 |
DBLP DOI BibTeX RDF |
Interrupt, Hardware accelerator |
61 | Ya-Shuai Lü, Li Shen 0007, Zhiying Wang 0003, Nong Xiao |
Dynamically utilizing computation accelerators for extensible processors in a software approach. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
computation accelerator, ASIP, dynamic binary translation |
61 | Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner |
Exploring the design space of LUT-based transparent accelerators. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
accelerator design, embedded processing, efficient computation |
58 | Sean Rul, Hans Vandierendonck, Koen De Bosschere |
Towards automatic program partitioning. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
off-loading, sub-algorithms, partitioning, accelerators |
58 | Jeff H. Derby, Robert K. Montoye, José E. Moreira |
VICTORIA: VMX indirect compute technology oriented towards in-line acceleration. |
Conf. Computing Frontiers |
2006 |
DBLP DOI BibTeX RDF |
VMX, SIMD, accelerators, powerPC |
54 | Samuel Williams 0001, Nathan Bell, Jee Whan Choi, Michael Garland, Leonid Oliker, Richard Vu |
Sparse Matrix-Vector Multiplication on Multicore and Accelerators. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
54 | Kaushik Datta, Samuel Williams 0001, Vasily Volkov, Jonathan Carter, Leonid Oliker, John Shalf, Katherine A. Yelick |
Auto-Tuning Stencil Computations on Multicore and Accelerators. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
51 | John H. Kelm, Steven S. Lumetta |
HybridOS: runtime support for reconfigurable accelerators. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
CPU/accelerator architecture, operating system, reconfigurable computing |
51 | Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier |
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
49 | José Carlos Sancho, Darren J. Kerbyson |
Dynamic Load Balancing of Matrix-Vector Multiplications on Roadrunner Compute Nodes. |
Euro-Par |
2009 |
DBLP DOI BibTeX RDF |
|
49 | Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner |
Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Manjunath Kudlur, Kevin Fan, Scott A. Mahlke |
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
system-level synthesis, loop accelerator, application-specific hardware |
42 | Hari Subramoni, Fabrizio Petrini, Virat Agarwal, Davide Pasetto |
High Performance Topology-Aware Communication in Multicore Processors. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Cecilia González-Alvarez, Harald Servat, Daniel Cabrera-Benitez, Xavier Aguilar, Carles Pons, Juan Fernández-Recio, Daniel Jiménez-González |
Drug Design on the Cell BE. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Ümit V. Çatalyürek, Renato Ferreira 0001, Timothy D. R. Hartley, George Teodoro, Rafael Sachetto Oliveira |
Data Flow Frameworks for Emerging Heterogeneous Architectures and Their Application to Biomedicine. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Dominik Göddeke, Robert Strzodka |
Mixed-Precision GPU-Multigrid Solvers with Strong Smoothers. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Stefan Turek, Dominik Göddeke, Sven H. M. Buijssen, Hilmar Wobker |
Hardware-Oriented Multigrid Finite Element Solvers on GPU-Accelerated Clusters. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Matthias Christen, Olaf Schenk, Esra Neufeld, Maarten M. Paulides, Helmar Burkhart |
Manycore Stencil Computations in Hyperthermia Applications. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Alex Chung Hen Chow, Gordon C. Fossum, Daniel A. Brokenshire |
Implementing FFTs on Multicore Architectures. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Jakub Kurzak, Jack J. Dongarra |
Implementing Matrix Factorizations on the Cell B. E. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Wesley Alvaro, Jakub Kurzak, Jack J. Dongarra |
Implementing Matrix Multiplication on the Cell B. E. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | David A. Bader, Virat Agarwal, Kamesh Madduri, Fabrizio Petrini |
Combinatorial Algorithm Design on the Cell/B.E. Processor. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Rajib Nath, Stanimire Tomov, Jack J. Dongarra |
BLAS for GPUs. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Laxmikant V. Kalé, David M. Kunzman, Lukasz Wesolowski |
Accelerator Support in the Charm++ Parallel Programming Model. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Abhinav Sarje, Jaroslaw Zola, Srinivas Aluru |
Pairwise Computations on the Cell Processor. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Stanimire Tomov, Jack J. Dongarra |
Dense Linear Algebra for Hybrid GPU-Based Systems. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Vipin Sachdeva, Michael Kistler, Tzy-Hwa Kathy Tzeng |
Enabling Bioinformatics Algorithms on the Cell/B.E. Processor. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Shubhabrata Sengupta, Mark J. Harris, Michael Garland, John D. Owens |
Efficient Parallel Scan Algorithms for Manycore GPUs. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | Virat Agarwal, David A. Bader |
Designing Fast Fourier Transform for the IBM Cell Broadband Engine. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
42 | John E. Stone, David J. Hardy, Barry Isralewitz, Klaus Schulten |
GPU Algorithms for Molecular Modeling. |
Scientific Computing with Multicore and Accelerators |
2010 |
DBLP DOI BibTeX RDF |
|
41 | Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén |
Programmable Accelerators for Reconfigurable Video Decoder. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull |
DVFS in loop accelerators using BLADES. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling |
41 | Walid A. Najjar |
Compiling code accelerators for FPGAs. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
41 | Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia |
Scalable subgraph mapping for acyclic computation accelerators. |
CASES |
2006 |
DBLP DOI BibTeX RDF |
compilation, embedded processors |
40 | Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton |
Petascale computing with accelerators. |
PPoPP |
2009 |
DBLP DOI BibTeX RDF |
hybrid programming models, accelerators |
40 | Lech Józwiak, Alexander Douglas |
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. |
ITNG |
2008 |
DBLP DOI BibTeX RDF |
re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool |
40 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
data-driven Xputer-based accelerators, CoDe-X, profiling-driven host/accelerator partitioning, resource-driven sequential/structural partitioning, accelerator source code, reconfigurable resources, C dialect, data-procedural language features, parallel programming, partitioning, performance optimization, hardware/software co-design, parallelizing programming environment |
40 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
39 | Evangelos Vlachos, Michelle L. Goodstein, Michael A. Kozuch, Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry |
ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications. |
ASPLOS |
2010 |
DBLP DOI BibTeX RDF |
hardware support for debugging, instruction-grain lifeguards, online parallel monitoring |
39 | Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich |
Impact of Loop Tiling on the Controller Logic of Acceleration Engines. |
ASAP |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Nagaraju Pothineni, Anshul Kumar, Kolin Paul |
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid |
Two-level microprocessor-accelerator partitioning. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Ajay V. Bhatt |
The Intel Geneseo Project. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Wei Wang, Qiang Wu, Wei Xie |
Hardware-Software Co-design for Dynamic Reconfigurable Computing with Collaborative Supports of Architecture and Operating System. |
CSCWD |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta |
High-performance, energy-efficient platforms using in-socket FPGA accelerators. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
in-socket accelerator, fpga, agility |
31 | Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick |
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose |
Scheduling dynamic parallelism on accelerators. |
Conf. Computing Frontiers |
2009 |
DBLP DOI BibTeX RDF |
cooperative scheduling, cell be |
31 | Toshio Endo, Satoshi Matsuoka |
Massive supercomputing coping with heterogeneity of modern accelerators. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Zdenek Vasícek, Lukás Sekanina |
Hardware Accelerators for Cartesian Genetic Programming. |
EuroGP |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Ya-Shuai Lü, Li Shen 0007, Libo Huang, Zhiying Wang 0003, Nong Xiao |
Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
subgraph covering, VLIW, ASIPs, extensible processors |
31 | Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas |
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman |
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. |
J. VLSI Signal Process. |
2002 |
DBLP DOI BibTeX RDF |
high-level hardware synthesis, automatic parallelization, datapath synthesis |
31 | Ricardo A. Fonseca, Luís O. Silva, Frank S. Tsung, Viktor K. Decyk, Wei Lu 0029, Chuang Ren, Warren B. Mori, S. Deng, S. Lee, Thomas C. Katsouleas, J. C. Adam |
OSIRIS: A Three-Dimensional, Fully Relativistic Particle in Cell Code for Modeling Plasma Based Accelerators. |
International Conference on Computational Science (3) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Andreas Adelmann, Derek Feichtinger |
Generic Large Scale 3D Visualization of Accelerators and Beam Lines. |
International Conference on Computational Science (3) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Kenneth J. Turner, Qian Bing |
Protocol Techniques for Testing Radiotherapy Accelerators. |
FORTE |
2002 |
DBLP DOI BibTeX RDF |
|
31 | James J. Feenan Jr., Patrick Fry, Ming Lei |
Clustering Web Accelerators. |
WECWIS |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider |
High-Level Synthesis of Nonprogrammable Hardware Accelerators. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Reiner W. Hartenstein, Jürgen Becker 0001 |
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. |
CODES |
1997 |
DBLP DOI BibTeX RDF |
structural programmable co-processors, design space exploration, performance estimation |
31 | Volodymyr V. Kindratenko, Robert B. Wilhelmson, Robert J. Brunner, Todd J. Martínez, Wen-mei W. Hwu |
High-Performance Computing with Accelerators. |
Comput. Sci. Eng. |
2010 |
DBLP DOI BibTeX RDF |
OpenMM, GPU, high-performance computing, OpenMP, accelerators |
31 | Lech Józwiak, Yahya Jan |
Architecture Design of Reconfigurable Accelerators for Demanding Applications. |
ITNG |
2010 |
DBLP DOI BibTeX RDF |
reconfigurable accelerators, advanced applications, design-space exploration, architecture design |
31 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). |
GPCE |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
31 | Karl M. Sammut, S. R. Jones |
Arithmetic Unit Design for Neural Accelerators: Cost Performance Issues. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
linear array accelerators, arithmetic constructs, instruction set measurements, cost/performance trade-offs, Neural networks |
29 | Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam |
Reconciling specialization and flexibility through compound circuits. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Tomoaki Hamano, Toshio Endo, Satoshi Matsuoka |
Power-aware dynamic task scheduling for heterogeneous accelerated clusters. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Sebastian Hessel, David Szczesny, Shadi Traboulsi, Attila Bilgic, Josef Hausner |
On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals. |
CSE (2) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Michael Gschwind |
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Jiri Kadlec, Roman Bartosinski, Martin Danek |
Accelerating Microblaze Floating Point Operations. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Josh Harr |
Innovative technologies II - Multi-paradigm computing. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Robert D. Ryne |
High energy physics - 25 years of accelerator modeling. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner |
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood |
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
29 | L. Louis Zhang, Qiang Wang, David M. Lewis |
Design of a VLIW Compute Accelerator on the Transmogrifier-2. |
FCCM |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Yahya Jan, Lech Józwiak |
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC |
29 | Vikas Aggarwal, Rafael García, Greg Stitt, Alan D. George, Herman Lam |
SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems. |
HPRCTA@SC |
2009 |
DBLP DOI BibTeX RDF |
communication, coordination, reconfigurable computing, productivity, portability, heterogeneous computing, accelerators |
29 | Charles F. Webb |
IBM z10: The Next-Generation Mainframe Microprocessor. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19 |
29 | Maurizio Paganini |
Nomadik®: A Mobile Multimedia Application Processor Platform. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
mobile multimedia application processor platform, Nomadik platform, industry standard host processor, low-power DSP, hardware accelerators |
29 | Pradip Bose |
Presilicon modeling: challenges in the late CMOS era. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS |
29 | Charlie Johnson, Jeff Welser |
Future processors: flexible and modular. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
multiprocessor, SoC, accelerators |
29 | Alberto Ferrante, Vincenzo Piuri, Fabien Castanier |
A QoS-enabled packet scheduling algorithm for IPSec multi-accelerator based systems. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
cryptographic accelerators, scheduling, QoS, quality of service, IPSec |
29 | Emil Jovanov, Veljko M. Milutinovic, Ali R. Hurson |
Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
nonnumeric processing, searching, sorting, hashing, hardware accelerators, Database operations |
23 | Md. Ashraful Islam, Kenji Kise |
Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators. |
HEART |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Christian Maximilian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker 0001 |
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators. |
HEART |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Yuka Sano, Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku |
Performance Evaluation on GPU-FPGA Accelerated Computing Considering Interconnections between Accelerators. |
HEART |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Kosuke Tatsumura |
Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation. |
HEART |
2021 |
DBLP DOI BibTeX RDF |
|
23 | James Thomas 0003, Chris Lavin, Alireza Kaviani |
Software-like Compilation for Data Center FPGA Accelerators. |
HEART |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Ceren Çubukçu Cerasi |
Teknoloji girişimi hızlandırıcılarının incelenmesi ve etkinliklerinin araştırılması: Türkiye\'deki hızlandırıcıların ampirik bir analizi (Research of technology startup accelerators and their effectiveness: an empirical analysis of accelerators in Turkey) |
|
2018 |
RDF |
|
23 | Kenji Kise |
Swap Based Merge Network for High Performance Sorting Accelerators. |
HEART |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Ioannis Stamoulias, Matthias Möller, Rene Miedema, Christos Strydis, Christoforos Kachris, Dimitrios Soudris |
High-Performance Hardware Accelerators for Solving Ordinary Differential Equations. |
HEART |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano |
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. |
HEART |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato |
Tightly Coupled Accelerators Architecture for Minimizing Communication Latency among Accelerators. |
IPDPS Workshops |
2013 |
DBLP DOI BibTeX RDF |
|
21 | John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel |
Cohesion: a hybrid memory model for accelerators. |
ISCA |
2010 |
DBLP DOI BibTeX RDF |
computer architecture, cache coherence, accelerator |
21 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. |
LCTES |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
21 | Frederico Pratas, Leonel Sousa |
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke |
Bridging the computation gap between programmable processors and hardwired accelerators. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
21 | David M. Kunzman, Laxmikant V. Kalé |
Towards a framework for abstracting accelerators in parallel applications: experience with cell. |
SC |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn |
Solving dense linear systems on platforms with multiple hardware accelerators. |
PPoPP |
2009 |
DBLP DOI BibTeX RDF |
algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus |
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