Search results for "asynchronous"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
62	Georgios Theodoropoulos 0001, J. V. Woods	Simulating Asynchronous Architectures on Transputer Networks.	PDP	1996	DBLP DOI BibTeX RDF	asynchronous architecture simulation, asynchronous design techniques, clock related timing problems, CSP based parallel language, asynchronous architectural simulation models, parallel architectures, logic design, asynchronous circuits, circuit analysis computing, parallel languages, Occam, Occam, asynchronous logic, transputer systems, transputer networks
53	Alexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum	Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Meng-Lin Yu, P. A. Subrahmanyam	Hazard-Free Asynchronous Circuit Synthesis.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Al Davis, Bill Coates 0001, Ken Stevens	Automatic Synthesis of Fast Compact Asynchronous Control Circuits.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli	Automated Synthesis of Asynchronous Interface Circuits.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Jim D. Garside	A CMOS VLSI Implementation of an Asynchronous ALU.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Kees van Berkel 0001, Ronan Burgess, Joep L. W. Kessels, Marly Roncken, Frits D. Schalij	Characterization and Evaluation of a Compiled Asynchronous IC.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
53	Jaco Haans, Kees van Berkel 0001, Ad M. G. Peeters, Frits D. Schalij	Asynchronous Multipliers as Combinational Handshake Circuits.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
49	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
49	Octavian Petre, Hans G. Kerkhoff	Scan Test Strategy for Asynchronous-Synchronous Interfaces.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test
48	Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har	Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	multiple outstanding transactions, in-order/out-of-order transaction completion, asynchronous on-chip bus, GALS
48	Rik van de Wiel	High-level test evaluation of asynchronous circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes
48	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
48	Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev	Low-latency asynchronous FIFO buffers.	ASYNC	1995	DBLP DOI BibTeX RDF	buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay
46	Venkatesh Akella, Ganesh Gopalakrishnan	Specification and Validation of Control-Intensive IC's in hopCP.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations
46	Stephen B. Furber, Martyn Edwards (eds.)	Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Ilana David, Ran Ginosar, Michael Yoeli	Self-Timed Architecture of a Reduced Instruction Set Computer.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Marly Roncken, Ronald Saeijs	Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	O. Salomon, Heinrich Klar	Self-Timed Fully Pipelined Multipliers.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Jo C. Ebergen, P. F. Bertrand, S. Gingras	Solving a Mutual Exclusion Problem with the RGD Arbiter.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Mark B. Josephs, Jan Tijmen Udding	Implementing a Stack as a Delay-insensitive Circuit.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup	Design of Self-timed Multipliers: A Comparison.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding	Normal Form in a Delay-Insensitive Algebra.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
46	Kees van Berkel 0001	VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power.	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
44	Pierre Ganty, Rupak Majumdar, Andrey Rybalchenko	Verifying liveness for asynchronous programs.	POPL	2009	DBLP DOI BibTeX RDF	asynchronous (event-driven) programming, fair termination, petri nets, liveness
44	Lilian Janin, Doug Edwards	Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.	IV	2005	DBLP DOI BibTeX RDF	program comprehension, asynchronous circuits, Software visualisation, coordinated views
44	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An Asynchronous Victim Cache.	DSD	2002	DBLP DOI BibTeX RDF	copy-back cache architecture, asynchronous design, victim cache
44	Rida A. Bazzi	Access cost for asynchronous Byzantine quorum systems.	Distributed Comput.	2001	DBLP DOI BibTeX RDF	Access cost, Fault tolerance, Distributed systems, Asynchronous, Quorum, Byzantine failures
44	Rida A. Bazzi	Non-blocking Asynchronous Byzantine Quorum Systems.	DISC	1999	DBLP DOI BibTeX RDF	access cost, distributed, asynchronous, failures, quorum, tolerance, Byzantine
44	Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand	A hybrid asynchronous system design environment.	ASYNC	1995	DBLP DOI BibTeX RDF	hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines
44	Chantal Ykman-Couvreur, Bill Lin 0001	Optimised state assignment for asynchronous circuit synthesis.	ASYNC	1995	DBLP DOI BibTeX RDF	optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment
44	David A. Kearney, Neil W. Bergmann	Performance evaluation of asynchronous logic pipelines with data dependent processing delays.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous logic pipelines, data dependent processing delays, logic stages, data dependent delay, two valued random variable, performance evaluation, performance evaluation, asynchronous circuits, pipeline processing, latches
43	Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton	A General Purpose Behavioural Asynchronous Synthesis System.	ASYNC	2004	DBLP DOI BibTeX RDF	Behavioural synthesis, asynchronous synthesis, cryptography
43	Joep L. W. Kessels, Paul Marston	Designing Asynchronous Standby Circuits for a Low-Power Pager.	ASYNC	1997	DBLP DOI BibTeX RDF	pager, loadable counter, synchronous/asynchronous, low-power, co-design
43	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver	AMULET2e: An Asynchronous Embedded Controller.	ASYNC	1997	DBLP DOI BibTeX RDF	Low power, Microprocessors, Asynchronous design, Embedded control
42	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
42	Thierry Chich, Pierre Fraigniaud	An extended comparison of slotted and unslotted deflection routing.	ICCCN	1997	DBLP DOI BibTeX RDF	slotted deflection routing, unslotted deflection routing, synchronized all-optical deflection networks, asynchronous all-optical deflection networks, synchronous mode, partially synchronous mode, asynchronous mode, fixed packet sizes, bound packet sizes, performances, design, cost, telecommunication network routing, bursty traffic
41	Chantal Ykman-Couvreur, Bill Lin 0001	Efficient state assignment framework for asynchronous state graphs.	ICCD	1995	DBLP DOI BibTeX RDF	state assignment framework, asynchronous state graphs, state graph level, complete state coding problem, circuit area, logic design, encoding, asynchronous circuits, asynchronous circuits, computation time, state assignment
41	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
41	Alain Girault, Clément Ménier	Automatic Production of Globally Asynchronous Locally Synchronous Systems.	EMSOFT	2002	DBLP DOI BibTeX RDF	Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution
40	José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo	Modelling Asynchronous Systems using Probability Distribution Functions.	PDP	2008	DBLP DOI BibTeX RDF	modelling, asynchronous, microarchitecture
40	Gaurav Gulati, Erik Brunvand	Design of a cell library for asynchronous microengines.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CMOS cell library, microprogramed control, asynchronous control, self-timed systems
40	John Teifel, Rajit Manohar	An Asynchronous Dataflow FPGA Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Asynchronous/synchronous operation, reconfigurable hardware, gate arrays, dataflow architectures
40	Lu Jun, Xianliang Lu, Han Hong, Qingsong Wei	A cooperative asynchronous write mechanism for NAS.	ACM SIGOPS Oper. Syst. Rev.	2002	DBLP DOI BibTeX RDF	performance, cache, cooperation, asynchronous, write, NAS
40	Hans M. Jacobson, Ganesh Gopalakrishnan	Asynchronous Microengines for Efficient High-level Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	asynchronous circuits, microprogramming, self-timing
40	Jing Wang	Asynchronous Computing and Communication Architecture Toward Energy Efficient Wireless Sensor Networks.	PerCom	2009	DBLP DOI BibTeX RDF
40	Morteza Damavandpeyma, Siamak Mohammadi	Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.	DSD	2008	DBLP DOI BibTeX RDF
40	C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven	Hades-towards the design of an asynchronous superscalar processor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
40	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
39	Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm	Applying Asynchronous Circuits in Contactless Smart Cards.	ASYNC	2000	DBLP DOI BibTeX RDF	low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
39	Romain Beauxis, Catuscia Palamidessi, Frank D. Valencia	On the Asynchronous Nature of the Asynchronous pi-Calculus.	Concurrency, Graphs and Models	2008	DBLP DOI BibTeX RDF
39	Mikio Aoyama, Akira Mori	A Unified Design Method of Asynchronous Service-Oriented Architecture Based on the Models and Patterns of Asynchronous Message Exchanges.	ICWS	2008	DBLP DOI BibTeX RDF
39	Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.	NOCS	2007	DBLP DOI BibTeX RDF
39	Ionel Muscalagiu, Hong Jiang, Horia Emil Popa	Implementation and Evaluation Model for the Asynchronous Search Techniques: From a Synchronously Distributed System to an Asynchronous Distributed System.	SYNASC	2006	DBLP DOI BibTeX RDF
39	Dietrich Kuske	Asynchronous Cellular Automata and Asynchronous Automata for Pomsets.	CONCUR	1998	DBLP DOI BibTeX RDF
38	Seokjin Kim, Ramalingam Sridhar	A local clocking approach for self-timed datapath designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
37	Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt	A new method for asynchronous pipeline control.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	asynchronous pipeline control, static logic control, dynamic logic control, flow controlled asynchronous method, asynchronous circuits, VLSI architecture
37	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
37	Karl M. Fant, Scott A. Brandt	NULL Convention LogicTM: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis.	ASAP	1996	DBLP DOI BibTeX RDF	consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic
37	Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick	Algorithms for the optimal state assignment of asynchronous state machines.	ARVLSI	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic
37	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
37	Jerry Zhigang Li, Sharon Elizabeth Bratt	Activity Theory as Tool for Analyzing Asynchronous Learning Networks (ALN).	ICWL	2004	DBLP DOI BibTeX RDF	online conference, E-learning, computer-mediated communication, Asynchronous communication, activity theory, instructional design, web-based learning, online discussion, Asynchronous Learning Networks
37	Atanu Chattopadhyay, Zeljko Zilic	A globally asynchronous locally dynamic system for ASICs and SoCs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design
37	François Verdier, Alain Mérigot, Bertrand Y. Zavidovique	Fast Stable Matching Algorithm using Asynchronous Parallel Programming Model.	CAMP	2000	DBLP DOI BibTeX RDF	fast stable matching algorithm, asynchronous parallel programming model, stable marriage algorithm, massively parallel asynchronous model, asynchronously communicating processors, image processing problem, image processing, 3D reconstruction, image matching, database search
37	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
37	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
37	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
37	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
36	Zuzana Beerliová-Trubíniová, Martin Hirt, Jesper Buus Nielsen	On the theoretical gap between synchronous and asynchronous MPC protocols.	PODC	2010	DBLP DOI BibTeX RDF	cryptography, multi-party computation, asynchronous network, mpc
36	Chun Sing Louis Tsui, John Q. Gan	Asynchronous BCI Control of a Robot Simulator with Supervised Online Training.	IDEAL	2007	DBLP DOI BibTeX RDF	asynchronous BCI, automated learning, Adaptation, brain-computer interface, online training
36	Prakash Chandrasekaran, Christopher L. Conway, Joseph M. Joy, Sriram K. Rajamani	Programming asynchronous layers with CLARITY.	ESEC/SIGSOFT FSE	2007	DBLP DOI BibTeX RDF	asynchronous components, design for analyzability, concurrency, static analysis, event-driven programming
36	Yoshihiro Nakaminami, Toshimitsu Masuzawa, Ted Herman	A Method for Evaluating Efficiency of Protocols on the Asynchronous Shared-State Model.	Self-Stabilizing Systems	2003	DBLP DOI BibTeX RDF	asynchronous model, synchronous execution, linear state-transition protocol, Distributed system, distributed algorithm, time complexity
36	Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor	Security Evaluation of Asynchronous Circuits.	CHES	2003	DBLP DOI BibTeX RDF	Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis
36	Yosi Ben-Asher, Esti Stein	Basic Algorithms for the Asynchronous Reconfigurable Mes.	IPDPS	2002	DBLP DOI BibTeX RDF	APRAM, Asynchronous, Reconfigurable mesh
36	Michel Hurfin, Michel Raynal	A Simple and Fast Asynchronous Consensus Protocol Based on a Weak Failure Detector.	Distributed Comput.	1999	DBLP DOI BibTeX RDF	Fault-tolerance, Asynchronous distributed systems, Crash failures, Unreliable failure detectors, Consensus problem
36	Mohsen Raji, Behnam Ghavami, Hossein Pedram	Statistical static performance analysis of asynchronous circuits considering process variation.	ISQED	2009	DBLP DOI BibTeX RDF
36	Kenneth Y. Yun	Recent Advances in Asynchronous Design Methodologies.	ASP-DAC	1999	DBLP DOI BibTeX RDF
36	Jun Gu, Ruchir Puri	Asynchronous circuit synthesis with Boolean satisfiability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
36	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
36	Eckhard Grass, Simon Jones	Asynchronous circuits based on multiple localised current-sensing completion detection.	ASYNC	1995	DBLP DOI BibTeX RDF	dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
36	Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt	ECSTAC: a fast asynchronous microprocessor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips
36	Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov	Designing an asynchronous pipeline token ring interface.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks
35	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
35	José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick	An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.	ASYNC	2002	DBLP DOI BibTeX RDF	PRML read channel, magnetic recording, asynchronous pipeline, digital arithmetic, FIR filter, dynamic logic, high-throughput, low-latency, distributed arithmetic, mixed timing
35	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
35	Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core.	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
35	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
35	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
35	D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao	Towards Asynchronous A-D Conversion.	ASYNC	1998	DBLP DOI BibTeX RDF	analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability
35	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
35	Hans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva	High-Level Asynchronous System Design Using the ACK Framework.	ASYNC	2000	DBLP DOI BibTeX RDF
34	Garth Baulch, David Hemmendinger, Cherrice Traver	Analyzing and verifying locally clocked circuits with the concurrency workbench.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
33	Anthony J. McAuley	Four State Asynchronous Architectures.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	four state asynchronous architectures, asynchronous wavefront array, one-dimensional multipliers, two-dimensional sorter, reliability, throughput, sequential circuits, many-valued logics, design complexity, asynchronous sequential logic
33	Weiguo Wang	An Asynchronous Two-Dimensional Self-Correcting Cellular Automaton	FOCS	1991	DBLP DOI BibTeX RDF	fault-free global synchronization clock, asynchronous two-dimensional self-correcting cellular automaton, arbitrary size, homogeneous asynchronous array, asynchronous environment, reliability, probability, reliable computation
33	Leonard R. Marino	The Effect of Asynchronous Inputs on Sequential Network Reliability.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Asynchronous arbiter, asynchronous sequential networks, flip-flop oscillations, inertial delay, input synchronization, metastable state, Schmitt trigger, synchronous sequential networks, reliability, asynchronous interactions
33	Achour Mostéfaoui, Sergio Rajsbaum, Michel Raynal	Synchronous condition-based consensus.	Distributed Comput.	2006	DBLP DOI BibTeX RDF	Early deciding, Consensus, Input vector, Synchronous distributed system, Process crash failure
33	Sufian Sudeng, Arthit Thongtak	Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	asynchronous control circuits, asynchronous DMA controller, template based technique, logic synthesis, Signal Transition Graph (STG)
33	Christof Fetzer	Perfect Failure Detection in Timed Asynchronous Systems.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Perfect failure detection, timed asynchronous system model, asynchronous distributed systems, crash failures
33	Victor Varshavsky, Vyacheslav Marakhovsky	GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor.	DELTA	2002	DBLP DOI BibTeX RDF	GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Synchronous Prototype, Arbitration, Asynchronous Design
33	Donna Dufner, Ojoung Kwon, William Rogers	Enriching Asynchronous Learning Networks through the Provision of Virtual Collaborative Learning Spaces: A Research Pilot.	HICSS	2001	DBLP DOI BibTeX RDF	Virtual Workgroup Environment, Web-enabled GDSS, Cooperative Document Production, Asynchronous Mode of Communication, Collaborative Learning, Distance Learning, Online Learning, Cooperative Learning, Collaboratories, Asynchronous Learning Networks