Search results for "bus-invert"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
106	Günter Knittel	Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels.	ITNG	2008	DBLP DOI BibTeX RDF	Bus-Invert Coding, Dual-Data-Rate, FPGA
103	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
93	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of application-specific systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
88	Rung-Bin Lin, Chi-Ming Tsai	Theoretical analysis of bus-invert coding.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
77	Rung-Bin Lin	Coupling reduction analysis of bus-invert coding.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
77	Rung-Bin Lin, Chi-Ming Tsai	Weight-Based Bus-Invert Coding for Low-Power Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
71	Shanq-Jang Ruan, Tsang-Chi Kan, Jih-Chieh Hsu	A novel crosstalk quantitative approach for simultaneously reducing power, noise, and delay based on bus-invert encoding schemes.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus-invert, coupling, interconnect delay
71	Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
67	Tina Lindkvist	Additional Knowledge of Bus Invert Coding Schemes.	IWSOC	2005	DBLP DOI BibTeX RDF
64	Jayapreetha Natesan, Damu Radhakrishnan	Shift Invert Coding (SINV) for Low Power VLSI.	DSD	2004	DBLP DOI BibTeX RDF
64	Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner	Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.	PATMOS	2006	DBLP DOI BibTeX RDF
62	Liang Deng, Martin D. F. Wong	Energy optimization in memory address bus structure for application-specific systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
60	Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger	Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.	DATE	2004	DBLP DOI BibTeX RDF
57	Haris Lekatsas, Jörg Henkel, Wayne H. Wolf	Approximate arithmetic coding for bus transition reduction in low power designs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
54	Unni Narayanan, Ki-Seok Chung, Taewhan Kim	Enhanced bus invert encodings for low-power.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
54	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
51	Vijay Sundararajan, Keshab K. Parhi	Reducing bus transition activity by limited weight coding with codeword slimming.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
50	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
49	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.	DELTA	2006	DBLP DOI BibTeX RDF	Simultaneous Switching Noise (SSN), Odd Simultaneous Transitions (OST), Even Simultaneous Transitions (EST), VLSI, Low power, Coding
46	Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira	Using Complementation and Resequencing to Minimize Transitions.	DAC	1998	DBLP DOI BibTeX RDF	reconfigurable computing, event-driven simulation
44	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
44	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
44	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.	ISLPED	2004	DBLP DOI BibTeX RDF
41	André K. Nieuwland, Atul Katoch, Daniele Rossi 0001, Cecilia Metra	Coding Techniques for Low Switching Noise in Fault Tolerant Busses.	IOLTS	2005	DBLP DOI BibTeX RDF
41	Ji Gu, Hui Guo 0001	An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction.	EURASIP J. Embed. Syst.	2009	DBLP DOI BibTeX RDF
41	Ji Gu, Hui Guo 0001	A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency.	ISCAS	2009	DBLP DOI BibTeX RDF
41	Myungchul Yoon, Byeong-Hee Roh	A Novel Low-Power Bus Design for Bus-Invert Coding.	IEICE Trans. Electron.	2007	DBLP DOI BibTeX RDF
41	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of system level bus.	ISLPED	1998	DBLP DOI BibTeX RDF
40	Haris Lekatsas, Jörg Henkel	ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	bus invert, low power, bus encoding
34	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.	VLSI Design	2008	DBLP DOI BibTeX RDF
34	Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram	Software-Only Bus Encoding Techniques for an Embedded System.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	memory bus encoding, bus activity minimization, CompactFlash, low power, Flash memory, LCD
34	Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang	Narrow bus encoding for low-power DSP systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
31	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos	Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.	CoRR	2023	DBLP DOI BibTeX RDF
31	Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos	Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating.	MOCAST	2023	DBLP DOI BibTeX RDF
31	M. Ali Vosoughi, Longfei Wang, Selçuk Köse	Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack.	SLIP	2019	DBLP DOI BibTeX RDF
31	Myungchul Yoon	Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
31	Melinda Y. Agyekum, Steven M. Nowick	A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication.	DATE	2011	DBLP DOI BibTeX RDF
31	Ni Zhou, Fei Qiao, Huazhong Yang, Hui Wang 0004	Low-Power Off-Chip Memory Design for Video Decoder Using Embedded Bus-Invert Coding.	ISADS	2011	DBLP DOI BibTeX RDF
31	Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys	Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
31	Fakhrul Zaman Rokhani, Wen-Chih Kan, John C. Kieffer, Gerald E. Sobelman	Optimality of Bus-Invert Coding.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
31	Rung-Bin Lin	Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
31	Alberto Aloisio, Paolo Branchini	Synchronous VME64x Block Transfers with Bus-Invert Coding For Low Noise, Low Power Performance.	ICIIS	2008	DBLP DOI BibTeX RDF
31	Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner	Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.	ReCoSoC	2007	DBLP BibTeX RDF
31	Sungpack Hong, Taewhan Kim, Unni Narayanan, Ki-Seok Chung	Decomposition of Bus-Invert Coding for Low-Power I/O.	J. Circuits Syst. Comput.	2000	DBLP DOI BibTeX RDF
28	Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
28	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Enric Musoll, Tomás Lang, Jordi Cortadella	Working-zone encoding for reducing the energy in microprocessor address buses.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
28	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
18	Fakhrul Zaman Rokhani, Gerald E. Sobelman	Low-Power Bus Transform Coding for Multilevel Signals.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Information-theoretic bounds on average signal transition activity [VLSI systems].	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
18	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Achievable bounds on signal transition activity.	ICCAD	1997	DBLP DOI BibTeX RDF	achievable bounds, busses, Low power, information theory, power estimation, CMOS circuits, switching activity