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Found 6 publication records. Showing 6 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
41 | Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra |
Power Consumption of Fault Tolerant Busses. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
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39 | Daniele Rossi 0001, André K. Nieuwland, Cecilia Metra |
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
bus layout, switching patterns, system reliability, IC, power supply network, simultaneous switching noise, coding techniques |
39 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
39 | Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen |
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
fault-tolerant, reliability, low power, coupling capacitance |
18 | Alok Agrawal, Rajesh Gupta 0002 |
Coordinated Control of Hybrid DERs Enabled Grid-Interactive Residential PCM With Hybrid Bus Layout. |
IEEE Syst. J. |
2022 |
DBLP DOI BibTeX RDF |
|
10 | Atul Katoch, Harry J. M. Veendrick, Evert Seevinck |
High speed current-mode signaling circuits for on-chip interconnects. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
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