Search results for "busses"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Himanshu Kaul, Jae-sun Seo, Mark A. Anders 0001, Dennis Sylvester, Ram Krishnamurthy 0001	A robust alternate repeater technique for high performance busses in the multi-core era.	ISCAS	2008	DBLP DOI BibTeX RDF
56	Ketan N. Patel, Igor L. Markov	Error-correction and crosstalk avoidance in DSM busses.	SLIP	2003	DBLP DOI BibTeX RDF	DSM busses, error-correction, crosstalk noise, bus encoding
52	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks.	ISCAS	2007	DBLP DOI BibTeX RDF
52	Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten	Routing of analog busses with parasitic symmetry.	ISPD	2005	DBLP DOI BibTeX RDF	analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
52	L. Di Silvio, Daniele Rossi 0001, Cecilia Metra	Crosstalk Effect Minimization for Encoded Busses.	IOLTS	2003	DBLP DOI BibTeX RDF
52	Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano	Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
52	Baher Haroun, Behzad Sajjadi	Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.	FPGA	1995	DBLP DOI BibTeX RDF
52	Friedhelm Meyer auf der Heide, Hieu Thien Pham	On the Performance of Networks with Multiple Busses.	STACS	1992	DBLP DOI BibTeX RDF
51	Nick A. Mould, Brian F. Veale, John K. Antonio, Monte P. Tull, John R. Junger	Design of steering vectors for dynamically reconfigurable architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
51	Wissam Hlayhel, Jacques Henri Collet, Laurent Fesquet	Implementing Snoop-Coherence Protocol for Future SMP Architectures.	Euro-Par	1999	DBLP DOI BibTeX RDF
42	Paul Metzgen, Dominic Nancekievill	Multiplexer restructuring for FPGA implementation cost reduction.	DAC	2005	DBLP DOI BibTeX RDF	busses, recoding, FPGA, synthesis, multiplexers, restructuring, logic optimization
42	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Achievable bounds on signal transition activity.	ICCAD	1997	DBLP DOI BibTeX RDF	achievable bounds, busses, Low power, information theory, power estimation, CMOS circuits, switching activity
42	C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal	A STAFAN-like functional testability measure for register-level circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	functional testability measure, register-level circuits, testability analysis programs, SCOAP, gate-level digital circuits, testability-driven synthesis, busses, F-STAFAN, Sun/SPARC workstation, performance evaluation, fault diagnosis, logic testing, high-level synthesis, statistical analysis, design for testability, fault simulation, fault coverage, circuit analysis computing, adders, multipliers, multiplexers, digital circuit, shift registers, logic gates, reliability theory, stuck-at fault model
39	Daniele Rossi 0001, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra	Power Consumption of Fault Tolerant Busses.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
39	Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten	Algorithms for automatic length compensation of busses in analog integrated circuits.	ISPD	2007	DBLP DOI BibTeX RDF	analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
39	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
39	Bassel Soudan	Reducing Inductive Coupling Skew in Wide Global Signal Busses.	DELTA	2006	DBLP DOI BibTeX RDF
39	André K. Nieuwland, Atul Katoch, Daniele Rossi 0001, Cecilia Metra	Coding Techniques for Low Switching Noise in Fault Tolerant Busses.	IOLTS	2005	DBLP DOI BibTeX RDF
39	Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow	Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions.	ITC	2004	DBLP DOI BibTeX RDF
39	E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
39	Helge Scheidig, M. F. Schneider, R. Spurk	Efficient and Scalable Logic Busses for Message-Passing Interconnection Networks.	EDMCC	1991	DBLP DOI BibTeX RDF
38	Ahmed Elkammar, Norman Scheinberg, Srinivasa Vemuru	Bus Encoding Scheme To Eliminate Unwanted Signal Transitions.	DELTA	2006	DBLP DOI BibTeX RDF
38	Håvard Kolle Riis, Philipp Häfliger	An Asynchronous 4-to-4 AER Mapper.	IWANN	2005	DBLP DOI BibTeX RDF
38	Marek Tudruj, Lukasz Masko	A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters.	PPAM	2001	DBLP DOI BibTeX RDF
38	Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet	Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Bandwidth requirement, SMP architecture, optical bus, shared bus
38	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Extensions to Programmable DSP architectures for Reduced Power Dissipation.	VLSI Design	1998	DBLP DOI BibTeX RDF	Low Power Design, DSP Architecture
38	Friedhelm Meyer auf der Heide, Klaus Schröder, Frank Schwarze	Routing on Networks of Optical Crossbars (Extended Abstract).	Euro-Par, Vol. I	1996	DBLP DOI BibTeX RDF
27	Luca Muratori, Lorenzo Peretto, Beatrice Pulvirenti, Raffaella Di Sante, Giovanni Bottiglieri, Federico Coiro	A vehicle integrated thermal management system for electric busses.	MetroAutomotive	2022	DBLP DOI BibTeX RDF
27	Markus Linnartz, Yasmin Dufner, Nicola Fricke	Information Presentation in Autonomous Shuttle Busses: -What and How?	ArtsIT	2021	DBLP DOI BibTeX RDF
27	Ubaid Mehmood, Irene Moser, Prem Prakash Jayaraman, Abhik Banerjee	Occupancy Estimation using WiFi: A Case Study for Counting Passengers on Busses.	WF-IoT	2019	DBLP DOI BibTeX RDF
27	Guilherme Valle Loures Brandão, Wilian Daniel Henriques do Amaral, Caio Augusto Rabite de Almeida, Jose Alberto Barroso Castañon	Simplified Thermal Comfort Evaluation on Public Busses for Performance Optimization.	HCI (20)	2017	DBLP DOI BibTeX RDF
27	Melike Erdogan, Ihsan Kaya	Evaluating Alternative-Fuel Busses for Public Transportation in Istanbul Using Interval Type-2 Fuzzy AHP and TOPSIS.	J. Multiple Valued Log. Soft Comput.	2016	DBLP BibTeX RDF
27	Sebastian Wagner, Gunter Nitzsche	Advanced steer-by-wire system for worlds longest busses.	ITSC	2016	DBLP DOI BibTeX RDF
27	Francesco Biral, Marco Galvani, Michele Zucchelli, Giuliano Giacomelli	Objective performance evaluation on mountain routes of diesel-electric hybrid busses.	ICM	2013	DBLP DOI BibTeX RDF
27	Bassel Soudan	The effect of SRNR on timing characteristics of signal busses.	ISQED	2011	DBLP DOI BibTeX RDF
27	Bassel Soudan	Reducing signal timing variations in inter-core busses.	Integr.	2010	DBLP DOI BibTeX RDF
27	Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli	A General Model of DPA Attacks to Precharged Busses in Symmetric-Key Cryptographic Algorithms.	ECCTD	2007	DBLP DOI BibTeX RDF
27	Rolf Ernst, Gernot Spiegelberg, Thomas Weber 0002, Hermann Kopetz, Alberto L. Sangiovanni-Vincentelli, Marek Jersak	Automotive networks: are new busses and gateways the answer or just another challenge?	CODES+ISSS	2007	DBLP DOI BibTeX RDF	automotive networks
27	Ketan N. Patel, Igor L. Markov	Error-correction and crosstalk avoidance in DSM busses.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
27	Bassel Soudan	Managing inductive coupling in wide signal busses.	ISCAS (2)	2004	DBLP BibTeX RDF
27	Daniele Rossi 0001, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra	Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems.	IOLTS	2004	DBLP DOI BibTeX RDF
27	Bassel Soudan	Reducing mutual inductance of wide signal busses through swizzling.	ICECS	2003	DBLP DOI BibTeX RDF
27	Abdelkader El Kamel, Jean-Yves Dieulot, Pierre Borne	Fuzzy controller for lateral guidance of busses.	ISIC	2002	DBLP DOI BibTeX RDF
27	William J. Buchanan	Computer busses - design and application.		2000	RDF
27	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	A coding framework for low-power address and data busses.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
27	Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj	Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.	VLSI Design	1998	DBLP DOI BibTeX RDF
27	Windsor W. Hsu, Jih-Kwon Peir	Busses.	The Computer Science and Engineering Handbook	1997	DBLP BibTeX RDF
27	Alberto Aloisio, S. Cavaliere, F. Cevenini, L. Merola, D. J. Fiore	Custom busses for large scale data acquisition systems.	ICECS	1996	DBLP DOI BibTeX RDF
27	Shlomo Kipnis	Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF
27	Mary L. Bailey, Michael A. Pagels, Kachung Kevin Wong	How using busses in multicomputer programs affects conservative parallel simulation.	PADS	1993	DBLP DOI BibTeX RDF
27	Roger B. Hughes, M. D. Francis, Simon Finn, Gerry Musgrave	Formal Tools in Tri-State Design in Busses.	TPHOLs	1992	DBLP BibTeX RDF
27	Shlomo Kipnis	Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses.	ICCD	1992	DBLP DOI BibTeX RDF
27	Christian Ewering	A New Allocation Method for the Synthesis of Partitioned Busses.	Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme	1990	DBLP DOI BibTeX RDF
27	K. Braun, Erwin M. Thurner	Designüberlegegungen und Konzept eines konfigurierbaren lokalen Busses für Spezialprozessoren.	ARCS	1990	DBLP BibTeX RDF
27	Christian Ewering	Automatic High Level Syntesis of Partitioned Busses.	ICCAD	1990	DBLP DOI BibTeX RDF
27	Zicheng Guo, Rami G. Melhem	Embedding pyramids in array processors with pipelined busses.	ASAP	1990	DBLP DOI BibTeX RDF
27	D. Simon	Finding the Trap Door Through Patent Protection of Busses.	COMPCON	1988	DBLP DOI BibTeX RDF
25	Sudeep Pasricha, Nikil D. Dutt	COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
25	Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton	GreenBus: a generic interconnect fabric for transaction level modelling.	DAC	2006	DBLP DOI BibTeX RDF	SoC, SystemC, TLM, on-chip communication
25	Brock J. LaMeres, Sunil P. Khatri	Performance model for inter-chip communication considering inductive cross-talk and cost.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
25	Atul Katoch, Harry J. M. Veendrick, Evert Seevinck	High speed current-mode signaling circuits for on-chip interconnects.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
25	A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson	Tester Architecture For The Source Synchronous Bus.	ITC	2004	DBLP DOI BibTeX RDF
25	Marek Tudruj, Lukasz Masko	Program Execution Control for Communication on the Fly in Dynamic Shared Memory Processor Clusters.	PARELEC	2002	DBLP DOI BibTeX RDF
25	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.	MTDT	2000	DBLP DOI BibTeX RDF
25	David J. Greaves	A Verilog to C Compiler.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF
25	Vijay Sundararajan, Keshab K. Parhi	Reducing bus transition activity by limited weight coding with codeword slimming.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
25	Michael Mock, Edgar Nett	Real-Time Communication in Autonomous Robot Systems.	ISADS	1999	DBLP DOI BibTeX RDF	multiple-access bus, TDMA, control system, real-time communication, robotic system
25	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Interconnect Diagnosis of Bus-Connected Multi-RAM Systems.	MTDT	1999	DBLP DOI BibTeX RDF
25	Ingrid Verbauwhede, Mihran Touriguian	A Low Power DSP Engine for Wireless Communications.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
25	Robert W. Horst	TNet: A Reliable System Area Network.	IEEE Micro	1995	DBLP DOI BibTeX RDF	TNet, routing, reliability, multiprocessor, wormhole routing, multistage interconnect network, flow control, I/O, system area network, massively parallel processing, IPC
13	Leonel Tedesco, Fabien Clermidy, Fernando Moraes 0001	A path-load based adaptive routing algorithm for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	quality of service, networks on chip, dynamic routing, traffic monitoring
13	Gunar Schirner, Rainer Dömer	Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	system-on-chip, System level design, transaction level modeling
13	Chunjie Duan, Sunil P. Khatri	Energy Efficient and High Speed On-Chip Ternary Bus.	DATE	2008	DBLP DOI BibTeX RDF
13	Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich	Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.	ARCS	2008	DBLP DOI BibTeX RDF
13	Marcel Nassar, Kapil Gulati, Arvind K. Sujeeth, Navid Aghasadeghi, Brian L. Evans, Keith R. Tinsley	Mitigating near-field interference in laptop embedded wireless transceivers.	ICASSP	2008	DBLP DOI BibTeX RDF
13	Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman	An Extensible I/O Subsystem.	FCCM	2008	DBLP DOI BibTeX RDF
13	Fahimeh Jafari, Mohammad Hossien Yaghmaee, Mohammad Sadegh Talebi, Ahmad Khonsari	Max-Min-Fair Best Effort Flow Control in Network-on-Chip Architectures.	ICCS (1)	2008	DBLP DOI BibTeX RDF	Network-on-Chip, flow control, Max-Min fairness
13	Abhisek Pan, James W. Tschanz, Sandip Kundu	A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit.	DFT	2008	DBLP DOI BibTeX RDF
13	Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals	A High-Speed Optical Multi-Drop Bus for Computer Interconnections.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
13	Kelly D. Larson	Translation of an existing VMM-based SystemVerilog testbench to OVM.	DAC	2008	DBLP DOI BibTeX RDF	OVM, VMM, testbenches, SystemVerilog
13	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
13	Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of a Dynamically Routed Processor Operand Network.	NOCS	2007	DBLP DOI BibTeX RDF
13	W. Mack Grady, Mehrdad Vatani, Ari Arapostathis	A new fault location method for electric power grids.	SCSC	2007	DBLP BibTeX RDF	electric power grids, voltage sags, fault location
13	Marieka Hoedemaeker, Mark A. Neerincx	Attuning In-Car User Interfaces to the Momentary Cognitive Load.	HCI (16)	2007	DBLP DOI BibTeX RDF	In-car services, central management, workload, adaptive user interface
13	Dimitrios N. Serpanos, Wayne H. Wolf	VLSI models of network-on-chip interconnect.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
13	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
13	Bradley R. Quinton, Steven J. E. Wilton	Embedded Programmable Logic Core Enhancements for System Bus Interfaces.	FPL	2007	DBLP DOI BibTeX RDF
13	Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat	NoC Implementation in FPGA Using Torus Topology.	FPL	2007	DBLP DOI BibTeX RDF
13	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han	Performance modeling for early analysis of multi-core systems.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling
13	Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy 0001	A robust edge encoding technique for energy-efficient multi-cycle interconnect.	ISLPED	2007	DBLP DOI BibTeX RDF	multi-cycle interconnect, interconnect, encoding, repeaters
13	Lochi Yu, Samar Abdi	Automatic SystemC TLM generation for custom communication platforms.	ICCD	2007	DBLP DOI BibTeX RDF
13	Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khonsari, Mohammad Hossien Yaghmaee	A Novel Congestion Control Scheme for Elastic Flows in Network-on-Chip Based on Sum-Rate Optimization.	ICCSA (3)	2007	DBLP DOI BibTeX RDF
13	Werner Hein, Jens Berkmann, Manfred Zimmermann, Mario Huemer	Object Oriented Signal Data Structures in VLSI Implementations of Wireless Modems.	EUROCAST	2007	DBLP DOI BibTeX RDF
13	Marek Tudruj, Lukasz Masko	Parallel Matrix Multiplication Based on Dynamic SMP Clusters in SoC Technology.	ISPA Workshops	2007	DBLP DOI BibTeX RDF
13	Patrick Leteinturier	Automotive semi-conductor trend & challenges.	DATE	2006	DBLP DOI BibTeX RDF
13	Brock J. LaMeres, Sunil P. Khatri	Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.	DATE	2006	DBLP DOI BibTeX RDF
13	Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski	A Graph Based Algorithm for Data Path Optimization in Custom Processors.	DSD	2006	DBLP DOI BibTeX RDF
13	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Constraint-driven bus matrix synthesis for MPSoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
13	Peter Sobe, Kathrin Peter	Construction of efficient OR-based deletion - tolerant coding schemes.	IPDPS	2006	DBLP DOI BibTeX RDF
13	Lukasz Masko, Gregory Mounie, Denis Trystram, Marek Tudruj	Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks.	PARELEC	2006	DBLP DOI BibTeX RDF