Search results for "capacitance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
99	Youngmin Kim, Dusan Petranovic, Dennis Sylvester	Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion.	ASP-DAC	2007	DBLP DOI BibTeX RDF	capacitance increment, metal fill insertion, inter level dielectric thickness planarity, metal dummy, signal capacitance, electrical characteristic, signal dimensions, dummy shape, dummy dimensions, simple test patterns, benchmark circuits, weighting function
92	Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa	Interconnect capacitance extraction for system LCD circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	interconnect capacitance, system LCD, capacitance extraction
80	Carlos Fernando Teodósio Soares, Antonio Petraglia	A systematic method to approximate capacitance ratios to improve capacitance matching in SC filters.	SBCCI	2007	DBLP DOI BibTeX RDF	capacitance matching, design method, switched-capacitor filters
75	Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong	Minimize the delay of parasitic capacitance and modeling in RLC circuit.	ICHIT	2009	DBLP DOI BibTeX RDF	Elmore, parasitic capacitance, delay, interconnection, oscillator
74	Hiroshi Yamamoto, Jeffrey A. Davis	Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
74	Andrew B. Kahng, Kambiz Samadi, Puneet Sharma	Study of Floating Fill Impact on Interconnect Capacitance.	ISQED	2006	DBLP DOI BibTeX RDF
70	X. Cai, Keith Nabors, Jacob K. White 0001	Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics.	ARVLSI	1995	DBLP DOI BibTeX RDF	piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
68	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	gate capacitance, low supply voltage, low-power design
66	Andrew Labun	Rapid method to account for process variation in full-chip capacitance extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
64	Srinivas Katkoori, Nand Kumar, Ranga Vemuri	High level profiling based low power synthesis technique.	ICCD	1995	DBLP DOI BibTeX RDF	high level profiling based low power synthesis technique, average switching capacitance, user-specified set, switching capacitance, VLSI, delay, logic design, power estimation, area
58	Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai	Parasitic capacitance modeling for multilevel interconnects.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
58	Peter J. Wright, Yung-Che Albert Shih	Capacitance of top leads metal - comparison between formula, simulation, and experiment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
53	Nihar R. Mohapatra, Arijit Dutta, Madhav P. Desai, V. Ramgopal Rao	Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics.	VLSI Design	2001	DBLP DOI BibTeX RDF
52	Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong	Variational capacitance modeling using orthogonal polynomial method.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	random variable reduction, process variations, capacitance extraction, orthogonal decomposition
52	Tarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger	Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters.	DAC	2008	DBLP DOI BibTeX RDF	sensitivity analysis, capacitance extraction, adjoint method
52	Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu 0001, Byron Krauter	A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.	DAC	2005	DBLP DOI BibTeX RDF	glitch propagation, noise analysis, effective capacitance
52	Yanhong Yuan, Prithviraj Banerjee	A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer.	IPDPS	2000	DBLP DOI BibTeX RDF	fast multipole algorithm, parallel algorithms, distributed memory multiprocessors, Capacitance extraction
52	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
51	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu	Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
51	Michael Ott, Jason Abt, Udit Sharma, Edward Keyes, Trevor J. Hall, Henry Schriemer	Quantitative Capacitance Measurements of MOS Structures using a Scanning Probe Microscope.	CCECE	2006	DBLP DOI BibTeX RDF
51	Weiping Shi, Fangqing Yu	A divide-and-conquer algorithm for 3-D capacitance extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
51	Fangqing Yu, Weiping Shi	A Divide-and-Conquer Algorithm for 3D Capacitance Extraction.	ISQED	2004	DBLP DOI BibTeX RDF
51	Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley	Measuring Stray Capacitance on Tester Hardware.	VTS	2002	DBLP DOI BibTeX RDF
51	Andrew B. Kahng, Sudhakar Muddu	Improved Effective Capacitance Computations for Use in Logic and Layout Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
51	Muhammad M. Khellah, Mohamed I. Elmasry	Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	low-power design, power estimation, high-level design
51	Michael W. Beattie, Lawrence T. Pileggi	Bounds for BEM Capacitance Extraction.	DAC	1997	DBLP DOI BibTeX RDF
48	Minoru Watanabe, Fuminori Kobayashi	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.35 micron, zero-overhead dynamic optically reconfigurable gate array VLSI, ZO-DORGA-VLSI, junction capacitance, photodiodes, load capacitance, configuration memory, CMOS process chip
48	Patrick F. Cummins, Geoffrey K. Vallis	Algorithm 732; solvers for self-adjoint elliptic problems in irregular two-dimensional domains.	ACM Trans. Math. Softw.	1994	DBLP DOI BibTeX RDF	capacitance iteration, capacitance matrix, fast Poisson solvers, Green's function, elliptic equations
47	Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter	Spatially distributed 3D circuit models.	DAC	2005	DBLP DOI BibTeX RDF	boundary element method (BEM), distributed circuit models, inverse inductance, capacitance
46	Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey	Yield evaluation of analog placement with arbitrary capacitor ratio.	ISQED	2009	DBLP DOI BibTeX RDF
46	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
45	Wenjian Yu, Chao Hu, Wangyang Zhang	Variational capacitance extraction of on-chip interconnects based on continuous surface model.	DAC	2009	DBLP DOI BibTeX RDF	geometric variation modeling, hermite polynomial chaos method, quadratic variation model, variational capacitance extraction, spatial correlation
45	Min Zhao 0001, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu	A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.	DAC	2006	DBLP DOI BibTeX RDF	sequence of linear programming, macromodeling, budgeting, decoupling capacitance
45	Hua Xiang 0001, Kai-Yuan Chao, Martin D. F. Wong	Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.	ISQED	2005	DBLP DOI BibTeX RDF	Layer migration, Max-cut, Capacitance coupling
45	Rong Jiang 0002, Yi-Hao Chang, Charlie Chung-Ping Chen	ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction.	DAC	2005	DBLP DOI BibTeX RDF	interconnect, iterative methods, extraction, boundary element method, capacitance, parasitic
45	Shu Yan, Vivek Sarin, Weiping Shi	Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics.	DAC	2004	DBLP DOI BibTeX RDF	interconnect, iterative methods, preconditioning, capacitance extraction
45	Jinsong Hou, Zeyi Wang, Xianlong Hong	The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.	ASP-DAC	1999	DBLP DOI BibTeX RDF	Parasitic Capacitance, Hierarchical h-Adaptive Computation, VLSI, Boundary Element Method
43	Rupesh S. Shelar	An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors.	ISPD	2009	DBLP DOI BibTeX RDF	routing, power, clock distribution
43	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung	On the feasibility of early routing capacitance estimation for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
43	Usha Narasimha, Anthony M. Hill, N. S. Nagaraj	SmartExtract: Accurate Capacitance Extraction for SOC Designs.	VLSI Design	2006	DBLP DOI BibTeX RDF
43	Di Wu 0017, Jiang Hu, Min Zhao 0001, Rabi N. Mahapatra	Timing driven track routing considering coupling capacitance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	S. B. Prakash, Pamela Abshire, M. Urdaneta, Elisabeth Smela	A CMOS capacitance sensor for cell adhesion characterization.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
43	Jason Helge Anderson, Farid N. Najm	Interconnect capacitance estimation for FPGAs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
43	Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen	Optimal spacing and capacitance padding for general clock structures.	ASP-DAC	2001	DBLP DOI BibTeX RDF
43	Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai	An On-Chip Coupling Capacitance Measurement Technique.	VLSI Design	2001	DBLP DOI BibTeX RDF
43	Michael W. Beattie, Lawrence T. Pileggi	Error bounds for capacitance extraction via window techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
43	Andrew B. Kahng, Sudhakar Muddu	New efficient algorithms for computing effective capacitance.	ISPD	1998	DBLP DOI BibTeX RDF
43	Keith Nabors, Jacob K. White 0001	FastCap: a multipole accelerated 3-D capacitance extraction program.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
41	Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Scan insertion criteria for low design impact.	VTS	1996	DBLP DOI BibTeX RDF	scan insertion criteria, design impact, flip-flop ordering, capacitance constraints, layout information, Italtel Design Environment, logic testing, integrated circuit testing, sequential circuits, automatic testing, application specific integrated circuits, logic CAD, flip-flops, integrated circuit design, power dissipation, partial scan, design flow, boundary scan testing, scan chain, capacitance, full scan
41	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
41	Stephen K. Sunter	A low cost 100 MHz analog test bus.	VTS	1995	DBLP DOI BibTeX RDF	analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
39	Bo Shen, Sunil P. Khatri, Takis Zourntos	Implementation of MOSFET based capacitors for digital applications.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	MOSFET capacitor, constant capacitance, reference capacitor
39	Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera	Effects of on-chip inductance on power distribution grid.	ISPD	2005	DBLP DOI BibTeX RDF	on-chip inductance, power supply noise, power distribution network, decoupling capacitance
38	Xiangyin Zeng, Jiangqi He, M. N. Abdulla, Qing-Lun Chen	Understanding and closed-form-formula determination of frequency-dependent bonding-pad characterization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
38	Mohsen Shavandi, Walied A. Moussa	Investigation of a 3-D Capacitor Micro Strain Gauge for Applications in Biomedical and Industrial Health Monitoring.	ICMENS	2004	DBLP DOI BibTeX RDF
38	Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap	RC delay metrics for performance optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
38	Murat R. Becer, Ibrahim N. Hajj	An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling.	ISQED	2000	DBLP DOI BibTeX RDF	delay, analytical model, decoupling, Crosstalk noise
38	Chris C. N. Chu, Martin D. F. Wong	A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
38	Chris C. N. Chu, D. F. Wong 0001	A new approach to simultaneous buffer insertion and wire sizing.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing
37	Wenwen Chai, Dan Jiao, Cheng-Kok Koh	A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction.	DAC	2009	DBLP DOI BibTeX RDF	full wave, integral-equation-based methods, capacitance extraction, direct solver
37	Fang Gong, Hao Yu 0001, Lei He 0001	PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.	DAC	2009	DBLP DOI BibTeX RDF	incremental precondition, parallel fast-multipole method, stochastic geometrical moments, capacitance extraction
37	Vittorio Ricchiuti	Power Bus Signal Integrity Improvement and EMI Mitigation on Multilayer High-Speed Digital PCBs with Embedded Capacitance.	IEEE Trans. Mob. Comput.	2003	DBLP DOI BibTeX RDF	Embedded capacitance, power bus, power/ground layers, power supply decoupling, electric field strength, S-parameters
37	Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai	A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.	ICCAD	1996	DBLP DOI BibTeX RDF	3D VLSI interconnects, DRT, Dimension Reduction Technique, FastCap, SPICELINK, dielectric layers, parallel signal lines, VLSI, capacitance extraction
36	Mosaddequr Rahman, Sazzadur Chowdhury	A Highly accurate method to calculate capacitance of MEMS sensors with circular membranes.	EIT	2009	DBLP DOI BibTeX RDF
36	Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, Jinjun Xiong	An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation.	DATE	2008	DBLP DOI BibTeX RDF
36	Liu Cai-feng, Wang Zhong-yu	A Novel Capacitance-Match Method for EAS Responder.	CSSE (6)	2008	DBLP DOI BibTeX RDF
36	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	design for manufacturability, dummy fill
36	Glenn H. Chapman, Vijay K. Jain	Defect Tolerance for a Capacitance Based Nanoscale Biosensor.	DFT	2008	DBLP DOI BibTeX RDF
36	Nima Shahbazi, Hamid Sarbazi-Azad	Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing.	ICPADS	2007	DBLP DOI BibTeX RDF
36	Tadashi Suetsugu, Marian K. Kazimierczuk	Output Characteristics of Class E Amplifier With Nonlinear Shunt Capacitance Versus Supply Voltage.	ISCAS	2007	DBLP DOI BibTeX RDF
36	Hua Xiang 0001, Kai-Yuan Chao, Martin D. F. Wong	An ECO routing algorithm for eliminating coupling-capacitance violations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Wenjian Yu, Mengsheng Zhang, Zeyi Wang	Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
36	Norberto Flores, Angel Fernando Kuri Morales, Carlos Gamio	An Application of Neural Networks for Image Reconstruction in Electrical Capacitance Tomography Applied to Oil Industry.	CIARP	2006	DBLP DOI BibTeX RDF
36	Guoqing Chen, Eby G. Friedman	Effective capacitance of RLC loads for estimating short-circuit power.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Sani R. Nassif, Kanak Agarwal, Emrah Acar	Methods for estimating decoupling capacitance of nonswitching circuit blocks.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Su-Jeong Sim, Jeongmin Park, Sung Min Park 0001	A 1.8V, 60dB Omega 11 GHz transimpedance amplifier with strong immunity to input parasitic capacitance.	ISCAS	2006	DBLP DOI BibTeX RDF
36	Randy Bach, Bob Davis, Rich Laubhan	Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
36	Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure	A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills.	VLSI Design	2006	DBLP DOI BibTeX RDF
36	Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Janusz Wozny	Simulation of Parasitic Interconnect Capacitance for Present and Future ICs.	International Conference on Computational Science (1)	2005	DBLP DOI BibTeX RDF
36	Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue	Effective capacitance for gate delay with RC loads.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
36	Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills.	ISQED	2005	DBLP DOI BibTeX RDF
36	Wenjian Yu, Zeyi Wang, Xianlong Hong	Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.	ICCD	2003	DBLP DOI BibTeX RDF
36	Sudhakar Bobba, Ibrahim N. Hajj	Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
36	Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage	Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	Tai-Yu Chou, Zoltan J. Cendes	Capacitance calculation of IC packages using the finite element method and planes of symmetry.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
36	Colin C. McAndrew, Bijan K. Bhattacharyya, Omar Wing	A Cinfinity-continuous depletion capacitance model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
36	Taoyun Wang, Joseph R. Mautz, Roger F. Harrington	The excess capacitance of a microstrip via in a dielectric substrate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
36	C. C. Christara, Elias N. Houstis, John R. Rice	A parallel spline collocation-capacitance method for elliptic partial differential equations.	ICS	1988	DBLP DOI BibTeX RDF	VAX
33	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
32	Youmin Guo, Zhenrui Peng	Comparative Study on Three Voidage Measurement Methods for Two-Phase Flow.	ISNN (3)	2009	DBLP DOI BibTeX RDF	Voidage measurement, Electrical Capacitance Tomography (ECT), Ant System Algorithm (ASA), Genetic Algorithm (GA), Least Squares Support Vector Machine (LS-SVM)
32	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
32	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance
32	Anantha P. Chandrakasan	Ultra low power digital signal processing.	VLSI Design	1996	DBLP DOI BibTeX RDF	ultra low power digital signal processing, portable wireless device, capacitance minimization, spatial signal correlations, temporal signal correlations, re-synchronization, operation reduction, 1 V, logic design, DSP, power consumption, switching, integrated circuit design, voltage scaling, digital signal processing chips, circuit optimisation, circuit design, data representation, circuit optimization, glitching, architecture optimization
30	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
30	Zheng Li, Ahalapitiya H. Jayatissa, Lash Mapa, Ezzatollah Salari, A. C. Jayasuriya	Electrochemical sensors for detection of biomolecules.	EIT	2009	DBLP DOI BibTeX RDF
30	Kang-Yeob Park, Wonseok Oh 0003, Boo-Young Choi, Jung-Won Han, S. M. Park	A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
30	Pilok Lim, Taewhan Kim	Thermal-aware high-level synthesis based on network flow method.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	power consumption, temperature, binding
30	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.	SLIP	2006	DBLP DOI BibTeX RDF	delay-balanced, minimal-power, interconnects, repeaters
30	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Jason Helge Anderson, Farid N. Najm	Power estimation techniques for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF