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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 64 occurrences of 50 keywords
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Results
Found 96 publication records. Showing 96 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
105 | Seiji Kajihara, Tsutomu Sasao |
On the Adders with Minimum Tests. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders |
103 | Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas |
Efficient Reversible Logic Design of BCD Subtractors. |
Trans. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
BCD subtractors, BCD adders, Reversible logic |
98 | Tomás Lang, Javier D. Bruguera |
Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Most significant carry, prefix tree, carry look-ahead adder |
84 | Robert W. Doran |
Variants of an Improved Carry Look-Ahead Adder. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
look-ahead carry, adder, adders, variation, improved, carry look-ahead adder |
84 | Himanshu Thapliyal, Sumedha K. Gupta |
Design of Novel Reversible Carry Look-Ahead BCD Subtractor. |
ICIT |
2006 |
DBLP DOI BibTeX RDF |
|
80 | Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos |
Diminished-One Modulo 2n+1 Adder Design. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders |
69 | Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos |
High-Speed Parallel-Prefix Modulo 2n-1 Adders. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders |
66 | Anum Khan, Arindom Chakraborty, Upal Barua Joy, Subodh Wairya, Mehedi Hasan |
Carry look-ahead and ripple carry method based 4-bit carry generator circuit for implementing wide-word length adder. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
60 | Bernd Becker 0001, Reiner Kolla |
On the Construction of Optimal Time Adders (Extended Abstract). |
STACS |
1988 |
DBLP DOI BibTeX RDF |
|
57 | Himanshu Thapliyal, M. B. Srinivas |
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Antonio Blotti, Maurizio Castellucci, Roberto Saletti |
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel |
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
52 | Andreas Herrfeld, Siegbert Hentschke |
Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
MVL, ternary adder, ternary multiplication, VLSI, multiple valued-logic |
51 | Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam |
A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
51 | Md. Ashik Zafar Dipto, Afran Sorwar, Elias Ahammad Sojib, Md. Mostak Tahmid Rangon |
Performance Improvement in Conventional 4-bit Static CMOS Carry Look-Ahead Adder by Modifying Carry-Generate and Propagate Terms. |
ICCCNT |
2020 |
DBLP DOI BibTeX RDF |
|
51 | Mehedi Hasan, Parag Biswas, Md. Shihabul Alam, Hasan U. Zaman, Mainul Hossain, Sharnali Islam |
High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder. |
ICCCNT |
2019 |
DBLP DOI BibTeX RDF |
|
51 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
51 | Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Zerina Begum, Mohd. Zulfiquar Hafiz |
Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders |
CoRR |
2010 |
DBLP BibTeX RDF |
|
51 | Gustavo A. Ruiz, Mercedes Granda |
An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit. |
Microelectron. J. |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga |
Design of High-Speed Floating Point Multiplier. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
FP operations, Fast Carry look ahead adder (MCLA), CSD algorithm, Booth algorithm |
48 | Nhon T. Quach, Michael J. Flynn |
High-Speed Addition in CMOS. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
high speed addition, static complementary metal-oxide semiconductor, Ling-type 32-bit adder, serial transistors, worst-case critical path, carry look-ahead, CMOS, adders, CMOS integrated circuits, gate delay, 32 bit |
48 | Binay Sugla, David A. Carlson |
Extreme Area-Time Tradeoffs in VLSI. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
bounded fan-in, fan-out prefix computation graphs, area requirements, constant factor reduction, area-time tradeoff, VLSI, lower bounds, digital arithmetic, layout, circuit layout CAD, carry look-ahead adder |
48 | Yang-Chang Hong, Thomas H. Payne |
Parallel Sorting in a Ring Network of Processors. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
ring network of processors, selection sorting algorithms, ring-connected array, item placement, carry-look-ahead techniques, computer networks, sorting, maintenance, manufacture, parallel implementation, performance improvement, inventory, parallel sorting |
48 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder |
48 | Dharma P. Agrawal |
High-Speed Arithmetic Arrays. |
IEEE Trans. Computers |
1979 |
DBLP DOI BibTeX RDF |
carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction |
44 | Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Low-Power Carry Skip Adder with Fast Saturation. |
ASAP |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Çetin Kaya Koç, Ching Yu Hung |
Bit-level systolic arrays for modular multiplication. |
J. VLSI Signal Process. |
1991 |
DBLP DOI BibTeX RDF |
sign estimation, scheduling, systolic array, modular multiplication, carry save adders |
36 | Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee |
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. |
Circuits Syst. Signal Process. |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Riley Jackson, Maxwell Phillips, Firas Hassan, Ahmed Ammar |
High Precision Carry-Look-Ahead Logic for Negation, Absolute Value, and Two's Complement. |
ICECS |
2023 |
DBLP DOI BibTeX RDF |
|
36 | Tomoyuki Tanaka, Christopher L. Ayala, Nobuyuki Yoshikawa |
A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic. |
IEICE Trans. Electron. |
2022 |
DBLP DOI BibTeX RDF |
|
36 | Sharana Basappa, P. Ravi Babu |
A low power architecture for 1D median filter using carry look ahead adder. |
Int. J. Adv. Intell. Paradigms |
2021 |
DBLP DOI BibTeX RDF |
|
36 | Bharat Garg, Sujit Kumar Patel |
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency. |
J. Signal Process. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
36 | Jianmin Wang, Fengqiu Liu, Yuhu Wu |
Stuck-at Fault Diagnosis of Four-bit Carry Look-ahead Adder by Shannon Expansion via Semi-tensor Product. |
SICE |
2021 |
DBLP BibTeX RDF |
|
36 | V. Muralidharan, N. Sathish Kumar |
Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder. |
Microprocess. Microsystems |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Hassan Afzali-Kusha, Mehdi Kamal, Massoud Pedram |
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique. |
ISQED |
2020 |
DBLP DOI BibTeX RDF |
|
36 | Tasneem AlSalem, Lina Nazzal, Marah Samara, Mawahib Hussein Sulieman |
Design and Simulation of 90 nm Threshold Logic Carry-Look-Ahead Adder. |
ACIT |
2019 |
DBLP DOI BibTeX RDF |
|
36 | Sara Ghafari, Morteza Mousazadeh, Abdollah Khoei, Ali Dadashi |
A New High-speed and Low area Efficient Pipelined 128-bit Adder Based on Modified Carry Look-ahead Merging with Han-Carlson Tree Method. |
MIXDES |
2019 |
DBLP DOI BibTeX RDF |
|
36 | A. Nagalakshmi, Ch. Sirisha, D. N. Madhusudana Rao |
Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
36 | Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
36 | Ioannis Voyiatzis, Costas Efstathiou |
SIC pair generation in near-optimal time with carry-look ahead adders. |
DTIS |
2018 |
DBLP DOI BibTeX RDF |
|
36 | Jabulani Nyathi, Abubaker Mutumba |
Slowing the none-critical path to improve carry look-ahead adder power dissipation. |
MWSCAS |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Pao-Lung Chen |
A low-cost carry look-ahead adder for flying-adder frequency synthesizer. |
ICCE-TW |
2016 |
DBLP DOI BibTeX RDF |
|
36 | Raj Johri, Shyam Akashe, Sanjay Sharma |
High performance 8 bit cascaded carry look ahead adder with precise power consumption. |
Int. J. Commun. Syst. |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Mojtaba Valinataj |
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors. |
Microelectron. Reliab. |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. |
ICICDT |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Nusrat Jahan Lisa, Hafiz Md. Hasan Babu |
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. |
VLSID |
2015 |
DBLP DOI BibTeX RDF |
|
36 | Himanshu Thapliyal, H. V. Jayashree, A. N. Nagamani, Hamid R. Arabnia |
Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. |
Trans. Comput. Sci. |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas |
New High-Speed Multioutput Carry Look-Ahead Adders. |
IEEE Trans. Circuits Syst. II Express Briefs |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Hafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen |
An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. |
SoCC |
2013 |
DBLP DOI BibTeX RDF |
|
36 | Itamar Levi, Ori Bass, Asaf Kaizerman, Alexander Belenky, Alexander Fish |
High speed Dual Mode Logic Carry Look Ahead Adder. |
ISCAS |
2012 |
DBLP DOI BibTeX RDF |
|
36 | P. H. S. T. Murthy, L. Madan Mohan, V. Sreenivasa Rao, V. Malleswara Rao |
4T Carry Look Ahead Adder Design Using MIFG. |
ICT |
2010 |
DBLP DOI BibTeX RDF |
|
36 | Alireza Namazi, Yasser Sedaghat, Seyed Ghassem Miremadi, Alireza Ejlali |
A low-cost fault-tolerant technique for Carry Look-Ahead adder. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas |
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Himanshu Thapliyal, Hamid R. Arabnia |
Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. |
CDES |
2006 |
DBLP BibTeX RDF |
|
36 | Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas |
Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture. |
AICCSA |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Bart Desoete, Alexis De Vos |
A reversible carry-look-ahead adder using control gates. |
Integr. |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko |
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. |
IEEE J. Solid State Circuits |
1996 |
DBLP DOI BibTeX RDF |
|
36 | James B. Kuo, Hung-Pin Chen 0001, H. J. Huang |
A BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
34 | Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis |
A Static Low-Power, High-Performance 32-bit Carry Skip Adder. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Ji-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim |
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Krister Landernäs, Johnny Holmberg, Mark Vesterbacka |
A high-speed low-latency digit-serial hybrid adder. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Feng Zhou, Peter Kornerup |
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. |
IEEE Symposium on Computer Arithmetic |
1995 |
DBLP DOI BibTeX RDF |
|
32 | Bernd Becker 0001 |
Efficient Testing of Optimal Time Adders (Extended Abstract). |
MFCS |
1986 |
DBLP DOI BibTeX RDF |
|
30 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Fast Low-Power 64-Bit Modular Hybrid Adder. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien |
Performance comparison of quantum-dot cellular automata adders. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman |
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
binary signed-digit number system, most significant carry detection, Sign detection |
25 | Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas |
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen |
Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Swapnil Bahl |
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas |
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. |
DFT |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
21 | Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002 |
An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications. |
Sci. China Ser. F Inf. Sci. |
2008 |
DBLP DOI BibTeX RDF |
number comparison, sign determination, overflow detection, VLSI, RNS, parity check |
21 | Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu |
The new architecture of radix-4 Chinese abacus adder. |
ISMVL |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis |
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Sheng Sun, Larry McMurchie, Carl Sechen |
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Bernd Becker 0001, Rolf Drechsler, Sudhakar M. Reddy |
(Quasi-) Linear Path Delay Fault Tests for Adders. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Tin Wai Kwan, Maitham Shams |
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic. |
ASYNC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer |
QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas |
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
ECDL, CMOS, adder, digital circuits |
16 | Ciaran McIvor, Máire McLoone, John V. McCanny |
FPGA Montgomery Multiplier Architectures - A Comparison. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Ciaran McIvor, Máire McLoone, John V. McCanny |
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | P. C. Chen, James B. Kuo |
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Bhushan A. Shinkre, James E. Stine |
A pipelined clock-delayed domino carry-lookahead adder. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim |
A Novel Clocking Strategy for Dynamic Circuits. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
VLSI circuits for low-power high-speed asynchronous addition. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Mohab Anis, Mohamed I. Elmasry |
Self-timed MOS current mode logic for digital applications. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Hong-Yi Huang, Teng-Neng Wang |
High-speed CMOS logic circuits in capacitor coupling technique. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Hamid Mahmoodi-Meimand, Ali Afzali-Kusha |
Efficient power clock generation for adiabatic logic. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Gin Yee, Carl Sechen |
Clock-delayed domino for dynamic circuit design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Mahmoud A. Manzoul |
Parallel CLA Algorithm for Fast Addition. |
PARELEC |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Aamir A. Farooqui, Vojin G. Oklobdzija |
VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Dinesh Somasekhar, Kaushik Roy 0001 |
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi |
DCT/IDCT processor for HDTV developed with dsp silicon compiler. |
J. VLSI Signal Process. |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Rajiv Jain, Alice C. Parker, Nohbyung Park |
Module Selection for Pipelined Synthesis. |
DAC |
1988 |
DBLP BibTeX RDF |
|
16 | Jagan P. Agrawal, V. Umapathi Reddy |
Log-sum multiplier. |
AFIPS National Computer Conference |
1976 |
DBLP DOI BibTeX RDF |
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