Search results for "carry-save"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
117	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
97	Mike Paterson, Nicholas Pippenger, Uri Zwick	Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions	FOCS	1990	DBLP DOI BibTeX RDF	multiplication circuits, multiple addition, shallowest possible circuits, shortest possible formulas, occurrence matrix, shortest multiple carry-save addition formulas, delay matrix, multiple carry-save adders, multiplication, symmetric Boolean functions, carry-save addition
93	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
84	Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders.	ICCD	1999	DBLP DOI BibTeX RDF	Booth algorithm, Carry-Save Adder and Wallace Tree, Multiplier
83	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
79	Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata	Efficient Implementation of Carry-Save Adders in FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
78	Junhyung Um, Taewhan Kim	An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	VLSI, arithmetic circuits, Carry-save-addition
74	Alexandre F. Tenca, Song Park, Lo'ai Ali Tawalbeh	Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Carry-save, arithmetic shift, computer arithmetic, redundant representation
72	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	The use of carry-save representation in joint module selection and retiming.	DAC	2000	DBLP DOI BibTeX RDF
72	Tobias G. Noll	Carry-save architectures for high-speed digital signal processing.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
65	Behrooz Parhami	Comments on "Evaluation of A + B + K Conditions Without Carry Propagation".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	carry-free circuit, A+B=K, negative effects, carry-save redundant numbers, (3, 2)-counters, carry propagation, carry-save numbers, pipeline processing, logic circuits, pipelined architectures, comparators, addition, parallel counters, redundant number representation, conditional branches
63	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	Mob. Networks Appl.	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
63	Stanislaw J. Piestrak	Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
63	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
62	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Optimal joint module-selection and retiming with carry-save representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
62	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
58	Viktor Bunimov, Manfred Schimmler	Area and Time Efficient Modular Multiplication of Large Integers.	ASAP	2003	DBLP DOI BibTeX RDF	Montgomery algorithm, interleaved modular multiplication, MSB-first arithmetic, redundant number arithmetic, Modular multiplication, carry save addition
56	Jean-Luc Beuchat, Jean-Michel Muller	Automatic Generation of Modular Multipliers for FPGA Applications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
56	Mark A. Erle, Michael J. Schulte	Decimal Multiplication Via Carry-Save Addition.	ASAP	2003	DBLP DOI BibTeX RDF
56	Paolo Montuschi, Luigi Ciminiera	n × n carry-save multipliers without final addition.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
52	Çetin Kaya Koç, Ching Yu Hung	Bit-level systolic arrays for modular multiplication.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF	sign estimation, scheduling, systolic array, modular multiplication, carry save adders
47	Levent Aksoy, Ece Olcay Günes	Area optimization algorithms in high-speed digital FIR filter synthesis.	SBCCI	2008	DBLP DOI BibTeX RDF	high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
46	Viv A. Bartlett, Andrew G. Dempster	Using carry-save adders in low-power multiplier blocks.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
46	Junhyung Um, Taewhan Kim, C. L. Liu 0001	Optimal allocation of carry-save-adders in arithmetic optimization.	ICCAD	1999	DBLP DOI BibTeX RDF
43	Ajay Kumar Verma, Paolo Ienne	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.	ASP-DAC	2007	DBLP DOI BibTeX RDF	multiplier-like circuits, XOR-dominated circuits, datapath design, netlist optimization, carry-save form, column compressors, XOR operations, logic synthesizers, algebraic factoring, computer arithmetic, logic synthesis, digital design, parallel multipliers
43	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
43	Viktor Bunimov, Manfred Schimmler	Efficient Parallel Multiplication Algorithm for Large Integres.	Euro-Par	2003	DBLP DOI BibTeX RDF	large number arithmetic, redundant numbers, Computer arithmetic, integer multiplication, carry save addition, parallel multiplication
43	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
43	S. Ramanathan, V. Visvanathan	A systolic architecture for LMS adaptive filtering with minimal adaptation delay.	VLSI Design	1996	DBLP DOI BibTeX RDF	LMS adaptive filtering, minimal adaptation delay, convergence behaviour, function preserving transformations, SFG representation, carry-save arithmetic, systolic folded pipelined architecture, VLSI, delays, systolic arrays, pipeline processing, adaptive filters, digital filters, digital signal processing chips, convergence of numerical methods, systolic architecture, signal flow graphs, signal flow graph, least mean squares methods, LMS algorithm
43	D. V. Poornaiah, P. V. Ananda Mohan	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications.	VLSI Design	1996	DBLP DOI BibTeX RDF	concurrent dual multiplier-dual adder architecture, video coding applications, high-throughput image coding, carry-save 4:2 compressors, computational complexity, VLSI, VLSI, data compression, video coding, adders, computation time, multiplying circuits, digital signal processing chips
43	Song Cui, Neil Burgess, Michael J. Liebelt, Kamran Eshraghian	A GaAs IEEE Floating Point Standard Single Precision Multiplier.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating point multiplier, rounding algorithm, modified carry save array, GaAs technology
41	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
41	Mark A. Erle, Michael J. Schulte, Brian J. Hickmann	Decimal Floating-Point Multiplication Via Carry-Save Addition.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
41	Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese	Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware.	DATE	2004	DBLP DOI BibTeX RDF
41	Ajay Kumar Verma, Paolo Ienne	Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.	ICCAD	2004	DBLP DOI BibTeX RDF
41	Youngtae Kim, Taewhan Kim	Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.	ASP-DAC	2001	DBLP DOI BibTeX RDF
41	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
41	Taewhan Kim, William Jao, Steven W. K. Tjiang	Circuit optimization using carry-save-adder cells.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
41	Taewhan Kim, William Jao, Steven W. K. Tjiang	Arithmetic Optimization Using Carry-Save-Adders.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
36	Jun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin	A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.	ISCAS	2007	DBLP DOI BibTeX RDF
32	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	Improved Design of High-Performance Parallel Decimal Multipliers.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Decimal multiplication, decimal carry-save addition, decimal codings, parallel multiplication
32	Naofumi Takagi	Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.	ISMVL	2002	DBLP DOI BibTeX RDF	carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
32	Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan	A New Divide and Conquer Method for Achieving High Speed Division in Hardware.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
32	Dhananjay S. Phatak, Tom Goff, Israel Koren	Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	constant-time addition, simultaneous format conversion, redundant adders, signed-digit addition, 4:2 compressor, Redundant representations, carry-save addition
32	Milos D. Ercegovac, Tomás Lang, Paolo Montuschi	Very-High Radix Division with Prescaling and Selection by Rounding.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	very-high radix division, quotient-digit selection, carry-save, computer arithmetic, digital arithmetic, selection, rounding, redundant representation, prescaling, carry logic, division algorithm
32	Jean Duprat, Jean-Michel Muller	The CORDIC Algorithm: New Results for Fast VLSI Implementation.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm
32	Stamatis Vassiliadis, James Phillips, Bart Blaner	Interlock Collapsing ALU's.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	interlocked fixed point arithmetic logic unit, unsigned binary, binary logical operations, single instruction execution, machine cycle, architectural compatibility, parallel processing, digital arithmetic, adders, CMOS integrated circuits, CMOS technology, carry-save adder, carry-lookahead adder, two's complement
32	Luigi Ciminiera, Paolo Montuschi	Higher Radix Square Rooting.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	nonrestoring square root algorithms, feasible algorithms, digit set, radicand bits, starting value, partial remainder bits, digit selection, radix 4, carry-save, constraints, representation, digital arithmetic, bounds, number theory, radix
32	Tom Rhyne, Noel R. Strader II	A Signed Bit-Sequential Multiplier.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	VLSI signal processing circuits, Bit-sequential multiplication, Booth's algorithm, carry-save arithmetic, computer arithmetic
32	R. Gnanasekaran	On a Bit-Serial Input and Bit-Serial Output Multiplier.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	two's complement number representation, Add-shift multiplier, bit-sequential multiplier, on-line multiplication, carry-save addition
32	John H. Zurawski, J. B. Gosling	Design of High-Speed Digital Divider Units.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	uncommitted logic arrays (gate arrays), Borrow?save subtraction, carry?save addition, digital division, group subtractor, iterative division, digital arithmetic
32	Daniel E. Atkins, Shauchi Ong	Time-Component Complexity of Two Approaches to Multioperand Binary Addition.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
32	Dharma P. Agrawal	High-Speed Arithmetic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	carry-look-ahead, carry-save, pipelining, multiplication, division, Arrays, square-root, square, high-speed arithmetic, sign detection, multifunction
32	Paul W. Baker	Suggestion for a Fast Binary Sine/Cosine Generator.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	Cascaded carry-save adders, continued products, digital arithmetic, sines, cosines
31	Henrik Ohlsson, Oscar Gustafsson, Lars Wanhammar	Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
31	Junhyung Um, Taewhan Kim, C. L. Liu 0001	A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.	DAC	2000	DBLP DOI BibTeX RDF
31	Chang Nian Zhang, Behrooz A. Shirazi, David Y. Y. Yun	Computing multiple modulo summation (abstract only): a new algorithm, its VLSI designs and applications.	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
31	Melika Amiri, Massoud Dousti, Majid Mohammadi	Design and implementation of carry-save adder using quantum-dot cellular automata.	J. Supercomput.	2024	DBLP DOI BibTeX RDF
31	Oleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos	Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition.	ICCAD	2022	DBLP DOI BibTeX RDF
31	Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini	An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
31	Raffaele De Rose, Paul Romero, Marco Lanuzza	Double-precision Dual Mode Logic carry-save multiplier.	Integr.	2019	DBLP DOI BibTeX RDF
31	Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik	A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
31	Debashis De, Jadav Chandra Das	Design of novel carry save adder using quantum dot-cellular automata.	J. Comput. Sci.	2017	DBLP DOI BibTeX RDF
31	Daniel Dinu, Johann Großschädl, Yann Le Corre	Efficient Masking of ARX-Based Block Ciphers Using Carry-Save Addition on Boolean Shares.	ISC	2017	DBLP DOI BibTeX RDF
31	Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo	On the use of approximate adders in carry-save multiplier-accumulators.	ISCAS	2017	DBLP DOI BibTeX RDF
31	Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis 0001, Kiamal Z. Pekmestzi	Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
31	Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik	A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
31	Ugur Cini, Olcay Kurt	MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding.	DTIS	2016	DBLP DOI BibTeX RDF
31	Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez	A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
31	Song Jia, Shigong Lyu, Xiayu Li, Li Liu, Yandong He	Simplified carry save adder-based array multiplier scheme and circuits design.	Int. J. Circuit Theory Appl.	2015	DBLP DOI BibTeX RDF
31	Ugur Cini, Olcay Kurt	A MAC unit with double carry-save scheme suitable for 6-input LUT based reconfigurable systems.	ICECS	2015	DBLP DOI BibTeX RDF
31	Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo	High Speed Speculative Multipliers Based on Speculative Carry-Save Tree.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
31	Minas Dasygenis	Generation and validation of multioperand carry save adders from the web.	DTIS	2014	DBLP DOI BibTeX RDF
31	Yanxiang Huang, Ajay Kapoor, Robert Rutten, José Pineda de Gyvez	A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers.	NORCHIP	2013	DBLP DOI BibTeX RDF
31	Stefan Siegel, Jürgen Wolff von Gudenberg	A long accumulator like a carry-save adder.	Computing	2012	DBLP DOI BibTeX RDF
31	David Neuhäuser	Design and evaluation of computer arithemetic based on carry-save and signed-digit redundant number representations.		2012	RDF
31	Carlos Diego Moreno-Moreno, Pilar Martínez, Francisco Bellido 0001, Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002	Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers.	IT Revolutions	2011	DBLP DOI BibTeX RDF
31	Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Improving FPGA Performance for Carry-Save Arithmetic.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
31	Amit Verma 0002, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.	FPL	2010	DBLP DOI BibTeX RDF
31	Anton Blad, Oscar Gustafsson	Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees.	ISCAS	2010	DBLP DOI BibTeX RDF
31	Roberto Gutierrez, Javier Valls, Asuncion Perez-Pascual	FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.	FPL	2009	DBLP DOI BibTeX RDF
31	Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi	Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic.	ICECS	2007	DBLP DOI BibTeX RDF
31	Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar	Multiplier blocks using carry-save adders.	ISCAS (2)	2004	DBLP BibTeX RDF
31	Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka	A low latency and low power dynamic Carry Save Adder.	ISCAS (2)	2004	DBLP BibTeX RDF
31	David Defour, Florent de Dinechin	Software Carry-Save: A Case Study for Instruction-Level Parallelism.	PaCT	2003	DBLP DOI BibTeX RDF
31	Zhan Yu, Meng-Lin Yu, Alan N. Willson Jr.	Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits.	DAC	2001	DBLP DOI BibTeX RDF
31	Youngtae Kim, Taewhan Kim	An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.	J. Circuits Syst. Comput.	2000	DBLP DOI BibTeX RDF
31	Taewhan Kim, Junhyung Um	A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).	ASP-DAC	2000	DBLP DOI BibTeX RDF
31	Wen-Chang Yeh, Chein-Wei Jen	A high performance carry-save to signed-digit recoder for fused addition-multiplication.	ICASSP	2000	DBLP DOI BibTeX RDF
31	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Efficient implementation of FIR filters using bit-level optimized carry-save additions.	EUSIPCO	2000	DBLP BibTeX RDF
31	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Joint module selection and retiming with carry-save representation.	EUSIPCO	2000	DBLP BibTeX RDF
31	Luigi Ciminiera, Paolo Montuschi	Carry-Save Multiplication Schemes without Final Addition.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF
31	Patrik Larsson, Chris J. Nicol	Transition reduction in carry-save adder trees.	ISLPED	1996	DBLP DOI BibTeX RDF
31	David R. Bull, Graham Wacey	Gate Level Optimisation of Primitive Operator Digital Filters using a Carry Save Decomposition.	ISCAS	1994	DBLP DOI BibTeX RDF
31	Damian Harris-Dowsett, Steve Summerfield	Carry Save & Pipelining Techniques for Wave Digital Filters.	ISCAS	1994	DBLP DOI BibTeX RDF
31	Stanislaw J. Piestrak	Design of residue generators and multioperand modular adders using carry-save adders.	IEEE Symposium on Computer Arithmetic	1991	DBLP DOI BibTeX RDF
31	Hung Chi Lai	A Study of Current Logic Design Problems: Part I, Design of Diagnosable Mos Networks; Part Ii, Minimum Nor (Nand) Networks for Parity Functions of an Arbitrary Number of Variables; Part Iii, Minimum Parallel Binary Adders With Nor (Nand) Gates and Their Extensions to Networks Consisting of Carry-Save Adders		1976	RDF
31	Dhiraj K. Pradhan	Fault-Tolerant Carry-Save Adders.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
30	Sudhakar Maddi, M. B. Srinivas	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.	SBCCI	2007	DBLP DOI BibTeX RDF	sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
25	Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin	A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF