Search results for "chips"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
57	Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki	Experimental fault analysis of 1 Mb SRAM chips.	VTS	1997	DBLP DOI BibTeX RDF	stuck-at cell faults, stuck-at bit-line faults, stuck-at word-line fault, neighborhood-pattern-sensitive faults, load capacity, margin fault detection, 1 Mbit, 70 C, 30 pF, memory testing, fault analysis, SRAM chips, SRAM chips
54	Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash	Panel discussions: "Cool chips for the next decade".	COOL Chips	2017	DBLP DOI BibTeX RDF
54	Zoran Nikolic, Rama Venkatasubramanian, Jason A. T. Jones, Peter Labaziewicz	A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA.	Hot Chips Symposium	2015	DBLP DOI BibTeX RDF
52	Louis Monier, Ramsey W. Haddad, Jeremy Dion	Recursive layout generation.	ARVLSI	1995	DBLP DOI BibTeX RDF	BiCMOS digital integrated circuits, recursive layout generation, layout directives, netlist description, hand-drawn layout, synthesized layout, overall layout, dense VLSI, VLSI, logic CAD, circuit layout CAD, microprocessor chips, microprocessor chips, VLSI chips, seamless integration
51	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A methodology for mapping multiple use-cases onto networks on chips.	DATE	2006	DBLP DOI BibTeX RDF	dynamic re-configuration, systems on chips, networks on chips, use-cases, modes
51	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	Mapping and configuration methods for multi-use-case networks on chips.	ASP-DAC	2006	DBLP DOI BibTeX RDF	guaranteed throughput, multiple application platforms, systems on chips, networks on chips, reconfiguration, dynamic, use-cases, voltage scaling, frequency scaling, best effort
50	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
50	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu	An FPGA-based re-configurable functional tester for memory chips.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits
45	John Sell, Alan Jay Smith	Guest Editors' Introduction: Hot Chips 17.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Hot Chips, Hot Chips 17, IEEE Micro March-April 2006
45	Chi-Min Lin, Tien-Fu Chen	Dynamic memory management for real-time embedded Java chips.	RTCSA	2000	DBLP DOI BibTeX RDF	storage management chips, dynamic runtime memory management, real-time embedded Java chips, CPU design, hardware-assisted scheme, dynamic garbage collection mechanism, predictable memory allocation time, data transition events, circular heap, simulation, Java, embedded systems, response time, memory architecture, memory architecture, storage allocation, coprocessors, resource constraints, real-time constraints, co-processor
43	José L. Ayala, Arvind Sridhar, Vinod Pangracious, David Atienza, Yusuf Leblebici	Through Silicon Via-Based Grid for Thermal Control in 3D Chips.	NanoNet	2009	DBLP DOI BibTeX RDF
43	Meng-Chiou Wu, Rung-Bin Lin	Reticle floorplanning of flexible chips for multi-project wafers.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	mask cost, multi-project wafer, reticle floorplanning, dicing
43	Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu	Testing of programmable analog neural network chips.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
42	Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer	An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.	VTS	2006	DBLP DOI BibTeX RDF
42	Jen-Fa Huang, Yao-Tang Chang, Chuen-Ching Wang	Reductions of Multiple-Access and Optical Beat Interference with Fiber-Grating OCDMA Balanced Decoder.	AINA	2003	DBLP DOI BibTeX RDF
42	Charles L. Seitz	Silicon Adventures-Go Ahead; Be Bold!	ARVLSI	1999	DBLP DOI BibTeX RDF
42	Prathima Agrawal, Frederick L. Cohen, Chet A. Palesko, Hung-Fai Stephen Law, Mark Miller, Mike Price, David W. Smith, Nicholas P. Van Brunt	Workstations (panel discussion): a complete solution to the VLSI designer?	DAC	1985	DBLP DOI BibTeX RDF
41		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Anawin Opasatian, Makoto Ikeda	Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Viktor Razilov, Juncen Zhong, Emil Matús, Gerhard P. Fettweis	Dual Vector Load for Improved Pipelining in Vector Processors.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Infall Syafalni, Mohamad Imam Firdaus, Andi M. Riyadhus Ilmy, Nana Sutisna, Trio Adiono	MazeCov-Q: An Efficient Maze-Based Reinforcement Learning Accelerator for Coverage.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura	Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai	Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo	A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Tobias Kaiser, Friedel Gerfers	A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Tatsuya Kubo, Shinya Takamaeda-Yamazaki	Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Takeshi Ohkawa, Masahiro Aoyagi	FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Jinsung Yoon, Donghyun Lee, Neungyun Kim, Su-Jung Lee, Gil-Ho Kwak, Tae-Hwan Kim	A Real-Time Keyword Spotting System Based on an End-To-End Binary Convolutional Neural Network in FPGA.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41	Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo	COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
41		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2022, Tokyo, Japan, April 20-22, 2022	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Moritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer 0001, Luca Benini	A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Yang Chen, Lin Liu, Xuelin Feng, Jinglin Shi	DXT501: An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano	Body Bias Control on a CGRA based on Convex Optimization.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Kaoru Masada, Ryohei Nakayama, Makoto Ikeda	Hardware Acceleration of Aggregate Signature Generation and Authentication by BLS Signature over BLS12-381 curve.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano	Power Analysis of Directly-connected FPGA Clusters.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato 0001, Hiroe Iwasaki, Hiroaki Kobayashi	An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo	A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Shine Parekkadan Sunny, Satyajit Das	Reinforcement Learning based Efficient Mapping of DNN Models onto Accelerators.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Hoang Gia Vu, Ngoc-Dai Bui	Encoder-based Many-Pattern Matching on FPGAs.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Yasuhiro Mochida, Daisuke Shirai, Koichi Takasugi	Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation Configuration.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41	Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima	A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
41		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano	Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo	An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato 0001, Kazuhiko Komatsu, Hiroaki Kobayashi	A Metadata Prefetching Mechanism for Hybrid Memory Architectures.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato	Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima	High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Ayan Datta, Karanvir Singh, Arpita Dutta, Kousik Debnath	A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Zhenshan Bao, Kang Zhan, Wenbo Zhang 0003, Junnan Guo	LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima	Training Low-Latency Spiking Neural Network through Knowledge Distillation.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41	Stanislav Sedukhin, Yoichi Tomioka, Kohei Yamamoto	In Search of the Performance- and Energy-Efficient CNN Accelerators.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
41		2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020	COOL CHIPS	2020	DBLP BibTeX RDF
41		Hot Chips 2020 Posters.	Hot Chips Symposium	2020	DBLP DOI BibTeX RDF
41	Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li 0007, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson 0001	Google's Training Chips Revealed: TPUv2 and TPUv3.	Hot Chips Symposium	2020	DBLP DOI BibTeX RDF
41	Shota Nakabeppu, Yosuke Ide, Masahiko Takahashi, Yuta Tsukahara, Hiromi Suzuki, Haruki Shishido, Nobuyuki Yamasaki	Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai	A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi	Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Takuya Sakuma, Hiroki Matsutani	An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner	A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Jisu Kwon, Moon Gi Seok, Daejin Park	User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew J. Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Rämäkkö, Sofia Mäkikyrö, Lauri Koskinen	A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda	Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo	A Novel In-DRAM Accelerator Architecture for Binary Neural Network.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Yasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura	MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini	XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41	Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung	Tileable Monolithic ReRAM Memory Design.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
41		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2019, Yokohama, Japan, April 17-19, 2019	COOL CHIPS	2019	DBLP BibTeX RDF
41	Eitan Medina	Hot Chips 2019.	Hot Chips Symposium	2019	DBLP DOI BibTeX RDF
41	Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu	Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda	Multi-Level Packet Processing Caches.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano	Key-value Store Chip Design for Low Power Consumption.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Mulya Agung, Muhammad Alfian Amrizal, Ryusuke Egawa, Hiroyuki Takizawa	The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis	Statistical Access Interval Prediction for Tightly Coupled Memory Systems.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Swagath Venkataramani, Jungwook Choi, Wei Wang 0333, Vijayalakshmi Srinivasan, Moriyoshi Ohara, Kailash Gopalakrishnan	A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Yugo Yamauchi, Kazusa Musha, Hideharu Amano	Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani	Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Alberto Gianelli, Nick Iliev, Shamma Nasrin, Mariagrazia Graziano, Amit Ranjan Trivedi	Low Power Speaker Identification using Look Up-free Gaussian Mixture Model in CMOS.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto	Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Ravi Theja Gollapudi, Gokturk Yuksek, Kanad Ghose	Cache-Aware Dynamic Classification and Scheduling for Linux.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Yusuke Shirota, Satoshi Shirai, Tatsunori Kanai	Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory System.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Shinichi Sasaki, Asuka Maki, Daisuke Miyashita, Jun Deguchi	Post Training Weight Compression with Distribution-based Filter-wise Quantization Step.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41	Masayuki Sato 0001, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi	Perceptron-based Cache Bypassing for Way-Adaptable Caches.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
41		2018 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2018, Yokohama, Japan, April 18-20, 2018	COOL CHIPS	2018	DBLP BibTeX RDF
41	Ryosuke Kazami, Hayate Okuhara, Hideharu Amano	Design automation methodology of a critical path monitor for adaptive voltage controls.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Tetsuya Odajima, Yuetsu Kodama, Mitsuhisa Sato	Power performance analysis of ARM scalable vector extension.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Vinod Pangracious, Ranjitha Dash, Ashok Kumar Turuk	3D-cool: Design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal	Subthreshold logic for low-area and energy efficient true random number generator.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto	Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima	A programmable analog calculation unit for vector computations.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Andrawes Al Bahou, Geethan Karunaratne, Renzo Andri, Lukas Cavigelli, Luca Benini	XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz 0001	Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?".	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Masayuki Sato 0001, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi	An energy-aware set-level refreshing mechanism for eDRAM last-level caches.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner	ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima	EMAXVR: A programmable accelerator employing near ALU utilization to DSA.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41	Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham	A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
41		2017 IEEE Symposium in Low-Power and High-Speed Chips, COOL Chips 2017, Yokohama, Japan, April 19-21, 2017	COOL Chips	2017	DBLP BibTeX RDF
41	Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano	Leveraging asymmetric body bias control for low power LSI design.	COOL Chips	2017	DBLP DOI BibTeX RDF