Search results for "clocking"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Kuan-Ta Chen, Polly Huang, Chun-Ying Huang, Chin-Laung Lei	The impact of network variabilities on TCP clocking schemes.	INFOCOM	2005	DBLP DOI BibTeX RDF
94	Sanjukta Bhanja, Sudeep Sarkar	Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
81	Baris Taskin, Bo Hong	Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
81	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
81	Gill A. Pratt, John Nguyen	Distributed Synchronous Clocking.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
79	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki	Safe clocking for the setup and hold timing constraints in datapath synthesis.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ordered clocking, register assignment, datapath synthesis
79	Gill A. Pratt, John Nguyen	Distributed synchronous clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals
77	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
70	Ganesh Venkataraman, Jiang Hu, Frank Liu 0001, Cliff C. N. Sze	Integrated placement and skew optimization for rotary clocking.	DATE	2006	DBLP DOI BibTeX RDF
70	Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim	A Novel Clocking Strategy for Dynamic Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
68	N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar	A VLSI array architecture with dynamic frequency clocking.	ICCD	1996	DBLP DOI BibTeX RDF	VLSI array architecture, dynamic frequency clocking, linear VLSI array processor, DFLAP, power requirements, image processing, VLSI, throughput
60	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Two-Dimensional Schemes for Clocking/Timing of QCA Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
60	Ganesh Venkataraman, Jiang Hu, Frank Liu 0001	Integrated Placement and Skew Optimization for Rotary Clocking.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
60	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	42% power savings through glitch-reducing clocking strategy in a hearing aid application.	ISCAS	2006	DBLP DOI BibTeX RDF
60	Irith Pomeranz, Sudhakar M. Reddy	SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
58	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
58	Ahmed El-Amawy	Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	constant skew bound, arbitrarily large computing structures, communicating cells, skew upper bound, maximum clocking rate, 2-D mesh framework, node design, nonplanar structures, parallel architectures, stability, hypercubes, network topology, synchronisation, hypercube networks, clocks, clock skew, global synchronization
56	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
52	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	A Serial Memory by Quantum-Dot Cellular Automata (QCA).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	memory architecture, emerging technologies, QCA
52	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	Tile-based design of a serial memory in QCA.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	quantum computing, memory architecture, emerging technologies, QCA
50	Baris Taskin, Joseph Demaio, Owen Farell, Michael Hazeltine, Ryan Ketner	Custom topology rotary clock router with tree subnetworks.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Resonant rotary clocking, clock network design, multiphase synchronization, clock skew
50	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
50	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
49	Vinayak Honkote, Baris Taskin	Zero clock skew synchronization with rotary clocking technology.	ISQED	2009	DBLP DOI BibTeX RDF
49	Lin Zhang, Aaron Carpenter, Berkehan Ciftcioglu, Alok Garg, Michael C. Huang 0001, Hui Wu	Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
49	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
49	Christos A. Papachristou, Mehrdad Nourani, Mark Spining	A multiple clocking scheme for low-power RTL design.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
49	Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
49	Marios D. Dikaiakos, Kenneth Steiglitz	Comparison of tree and straight-line clocking for long systolic arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
49	Nohbyung Park, Alice C. Parker	Synthesis of optimal clocking schemes.	DAC	1985	DBLP DOI BibTeX RDF
47	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
47	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
42	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Synchronization of pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
40	Vinayak Honkote, Baris Taskin	PEEC based parasitic modeling for power analysis on custom rotary rings.	ISLPED	2010	DBLP DOI BibTeX RDF	resonant clocking, simulation, modeling, interconnect
40	Sultan Al-Hinai, Lynn Margaret Batten, Bernard D. Colbert, Kenneth Koon-Ho Wong	Algebraic Attacks on Clock-Controlled Stream Ciphers.	ACISP	2006	DBLP DOI BibTeX RDF	irregular clocking, stream cipher, linear feedback shift register, algebraic attack, clock control
40	Hans M. Jacobson	Improved clock-gating through transparent pipelining.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive pipeline depth, dynamic pipeline scaling, optimal pipeline clocking, pipeline stage unification, transparent pipeline, low power, high performance, microarchitecture, circuits, clock gating
40	Eric Filiol	Decimation Attack of Stream Ciphers.	INDOCRYPT	2000	DBLP DOI BibTeX RDF	sequence decimation, multiple clocking, Stream cipher, linear feedback shift register, correlation attack, fast correlation attack
39	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki	Safe clocking register assignment in datapath synthesis.	ICCD	2008	DBLP DOI BibTeX RDF
39	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-phase resonant clocking for ultra-low-power hearing aid applications.	DATE	2006	DBLP DOI BibTeX RDF
39	Nikola Nedovic, Vojin G. Oklobdzija	Dual-edge triggered storage elements and clocking strategy for low-power systems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
39	Min-Gyu Kim, Gil-Cho Ahn, Un-Ku Moon	An improved algorithmic ADC clocking scheme.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
39	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma	Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.	VLSI Design	2004	DBLP DOI BibTeX RDF
39	Ramalingam Sridhar	System-on-Chip (SoC): Clocking and Synchronization Issues.	VLSI Design	2004	DBLP DOI BibTeX RDF
39	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Energy recovery clocking scheme and flip-flops for ultra low-energy applications.	ISLPED	2003	DBLP DOI BibTeX RDF	flip-flop, clock, clock tree, energy recovery, adiabatic
39	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna	Datapath Scheduling using Dynamic Frequency Clocking.	ISVLSI	2002	DBLP DOI BibTeX RDF
39	Oswaldo Cadenas, Graham M. Megson	A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.	FPL	2002	DBLP DOI BibTeX RDF
39	Piet van Remortel, Tom Lenaerts, Bernard Manderick	The Robustness of Small Developped SBlock Circuits Using Different Clocking Schemes.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
39	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
39	Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung	A New Single-Clock Flip-Clop for Half-Swing Clocking.	ASP-DAC	1999	DBLP DOI BibTeX RDF
39	Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan	Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.	VLSI Design	1999	DBLP DOI BibTeX RDF
39	Mohamed Nekili, Guy Bois, Yvon Savaria	Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
39	Kenneth Y. Yun, Ryan P. Donohue	Pausible Clocking: A First Step Toward Heterogeneous Systems.	ICCD	1996	DBLP DOI BibTeX RDF
37	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	Clocking-Based Coplanar Wire Crossing Scheme for QCA.	VLSI Design	2010	DBLP DOI BibTeX RDF	Quantum Cellular Automata, Wire Crossing, Coplanar, Low Power, Clocking, Crossover, QCA, Quantum-dot Cellular Automata
37	Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis	Clocking structures and power analysis for nanomagnet-based logic devices.	ISLPED	2007	DBLP DOI BibTeX RDF	magnetic logic, nanotechnology, clocking, QCA
37	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional pre-charge techniques for power-efficient dual-edge clocking.	ISLPED	2002	DBLP DOI BibTeX RDF	clocked storage elements, dual edge-triggered flip-flop, power consumption, clocking, clock distribution
37	Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward	Rational clocking [digital systems design].	ICCD	1995	DBLP DOI BibTeX RDF	rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
37	Nohbyung Park, Alice C. Parker	Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	maximum execution overlap, high-speed digital systems, performance evaluation, data dependencies, clocking, clocks, digital systems, branching, resource conflicts
36	Fahim U. Rahman, Visvesh Sathe 0001	Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
36	David Trachtenherz	AutoFocus Stream Processing for Single-Clocking and Multi-Clocking Semantics.	Arch. Formal Proofs	2011	DBLP BibTeX RDF
36	Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian	Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus.	ICCAD	2011	DBLP DOI BibTeX RDF
36	Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki	Half-swing clocking scheme for 75% power saving in clocking circuitry.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
31	Maja Etinski, Julita Corbalán, Jesús Labarta, Mateo Valero, Alexander V. Veidenbaum	Power-aware load balancing of large scale MPI applications.	IPDPS	2009	DBLP DOI BibTeX RDF
31	Xiaojun Ma, Jing Huang 0001, Fabrizio Lombardi	A model for computing and energy dissipation of molecular QCA devices and circuits.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	thermodynamic analysis, emerging technology, reversible computing, QCA
31	Vinayak Honkote, Baris Taskin	Custom rotary clock router.	ICCD	2008	DBLP DOI BibTeX RDF
31	Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu 0001, Santhosh Kumar Pilakkat	Design of clocked circuits using UML.	ASP-DAC	2005	DBLP DOI BibTeX RDF
31	Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer	QCA-Based Majority Gate Design under Radius of Effect-Induced Faults.	DFT	2005	DBLP DOI BibTeX RDF
31	Oswaldo Cadenas, Graham M. Megson	Improving mW/MHz Ratio in FPGAs Pipelined Designs.	DSD	2002	DBLP DOI BibTeX RDF
31	Xiaohong Jiang 0001, Susumu Horiguchi	Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model.	DFT	2000	DBLP DOI BibTeX RDF
31	Mohit Aron, Peter Druschel	Soft timers: efficient microsecond software timer support for network processing.	SOSP	1999	DBLP DOI BibTeX RDF
31	Maheshwar Umasankar, Ahmed El-Amawy	Generalized Algorithms for Systematic Synthesis of Branch-and-Combine Clock Networks for Meshes, Tori, and Hypercubes.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	skew bound, Branch-and-Combine, feature cycle length, hypercube, mesh, tile, torus, Clock skew, clock network
29	Keisuke Inoue, Mineo Kaneko	A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	ordered clocking, resource assignment, datapath synthesis
29	Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo	A shift-register-based QCA memory architecture.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	clocking, Quantum-dot cellular automata, memory design
29	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
29	Hao Jiang, Constantinos Dovrolis	Why is the internet traffic bursty in short time scales?	SIGMETRICS	2005	DBLP DOI BibTeX RDF	ON-OFF model, TCP pacing, TCP self-clocking, wavelet-based multiresolution analysis, traffic modeling, burstiness
29	Slobodan Petrovic, Amparo Fúster-Sabater	Clock Control Sequence Reconstruction in the Ciphertext Only Attack Scenario.	ICICS	2004	DBLP DOI BibTeX RDF	Irregular clocking, Cryptanalysis, Edit distance, Correlation attack, Directed search
29	Kevin Chen, Leonie Ruth Simpson, Matthew Henricksen, William Millan, Ed Dawson	A Complete Divide and Conquer Attack on the Alpha1 Stream Cipher.	ICISC	2003	DBLP DOI BibTeX RDF	Alpha1, irregular clocking, divide and conquer attack, Cryptanalysis, stream cipher
29	Jovan Dj. Golic	Correlation Analysis of the Shrinking Generator.	CRYPTO	2001	DBLP DOI BibTeX RDF	unconstrained irregular clocking, Stream ciphers, fast correlation attacks, posterior probabilities
29	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
29	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
29	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Design tradeoffs in high speed multipliers and FIR filters.	VLSI Design	1996	DBLP DOI BibTeX RDF	high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed
29	Manish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain	Extraction of finite state machines from transistor netlists by symbolic simulation.	ICCD	1995	DBLP DOI BibTeX RDF	finite state machine extraction, transistor netlists, clock level finite state machines, gate level representation, circuit clocking, output timing, simulation patterns, next state, output function, equivalent FSM, static storage structures, time multiplexed inputs, time multiplexed outputs, finite state machines, logic design, logic CAD, circuit analysis computing, FSMs, symbolic simulation, symbolic simulator, Ordered Binary Decision Diagrams
29	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
29	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
28	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
28	Krister Jacobsson, Lachlan L. H. Andrew, Ao Tang, Karl Henrik Johansson, Håkan Hjalmarsson, Steven H. Low	ACK-Clocking Dynamics: Modelling the Interaction between Windows and the Network.	INFOCOM	2008	DBLP DOI BibTeX RDF
28	Chih-Yu Wen, Robin D. Morris, William A. Sethares	Distance Estimation Using Bidirectional Communications Without Synchronous Clocking.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
28	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud	Thermally robust clocking schemes for 3D integrated circuits.	DATE	2007	DBLP DOI BibTeX RDF
28	Chunsheng Liu, Vikram Iyengar	Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking.	DATE	2006	DBLP DOI BibTeX RDF
28	Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan	Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking.	VTS	2006	DBLP DOI BibTeX RDF
28	Mahdi Nazm Bojnordi, Nariman Moezzi Madani, Mehdi Semsarzadeh, Ali Afzali-Kusha	An Efficient Clocking Scheme for On-Chip Communications.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Scott Fairbanks, Simon W. Moore	Self-Timed Circuitry for Global Clocking.	ASYNC	2005	DBLP DOI BibTeX RDF
28	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
28	Wei Ling, Yvon Savaria	Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.	ISQED	2005	DBLP DOI BibTeX RDF
28	Chunsheng Liu, Vikram Iyengar, Jiangfan Shi, Érika F. Cota	Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking.	VTS	2005	DBLP DOI BibTeX RDF
28	Kirti Joshi, Eric W. MacDonald	Reduction of Instantaneous Power by Ripple Scan Clocking.	VTS	2005	DBLP DOI BibTeX RDF
28	Shih-Chang Hsia	A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems.	IWSOC	2003	DBLP DOI BibTeX RDF
28	Vojin G. Oklobdzija	Clocking and Clocked Storage Elements in Multi-GHz Environment.	PATMOS	2002	DBLP DOI BibTeX RDF
28	Arindam Mukherjee 0001, Kai Wang 0011, Lauren Hui Chen, Malgorzata Marek-Sadowska	Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.	DATE	2002	DBLP DOI BibTeX RDF
28	Kenneth Y. Yun, Ayoob E. Dooply	Optimal Evaluation Clocking of Self-Resetting Domino Pipelines.	ASP-DAC	1999	DBLP DOI BibTeX RDF
28	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS (1)	1999	DBLP DOI BibTeX RDF